Flash memory device, controller, and method capable of performing access operation upon data unit(s) of multiple planes of flash memory device in response one simplified command sequence

1. A flash memory controller to be used in a storage device and coupled to a flash memory device of the storage device through a specific communication interface, comprising:

an input/output ( 110 ) circuit, coupled to the flash memory device through the specific communication interface, for sending commands and data between the flash memory device and a processor; and

the processor, coupled to the I/O circuit, for controlling the I/O circuit sending a set-feature signal to the flash memory device to enable, disable, or configure an access operation of the flash memory device, to make the flash memory device perform the access operation to control the flash memory device generating second address information associated with a second plane of the flash memory device according to a first address information of a first plane of the flash memory device, and then selecting multiple data units at the first plane and the second plane based on the first address information and the second address information in response to an access command or a specific indication command so as to perform the access operation upon the multiple data units at the first plane and the second plane;

wherein the set-feature signal comprises a set-feature command and a feature information which is associated with the access operation; the access operation is a copy back read operation, an erase operation, or a write operation; and, the feature information comprises a parameter data; when the parameter data is set as a first logic bit, the access operation, to be performed by the flash memory device, is enabled and configured as a sequential mode which is arranged to sequentially access data units of the different planes of the flash memory device according to serial numbers of the different planes in response to the access command or the specific indication command sent from the flash memory controller.

2. The flash memory controller of claim 1 , wherein the processor is arranged to send the set-feature signal to the flash memory device to enable, disable, or configure the access operation of the flash memory device when the flash memory controller is powered on or the flash memory device is powered on.

3. The flash memory controller of claim 1 wherein when the parameter data is set as a second logic bit, the access operation of the flash memory device is disabled.

4. The flash memory controller of claim 1 , wherein the feature information comprises another parameter data; when the another parameter data is set as a first logic bit, the access operation, to be performed by the flash memory device, is configured to be performed according to a bit map information which is calculated and stored by the flash memory device.

5. The flash memory controller of claim 4 , wherein when another the parameter data is set as a second logic bit, the access operation of the flash memory device is performed according to an updated bit map information sent from the flash memory controller.

6. The flash memory controller of claim 1 , wherein the feature information comprises another parameter data; when the another parameter data is set as a first logic bit, the access operation, to be performed by the flash memory device, is configured to be performed in response to the specific indication sent from the flash memory controller; and, when the another parameter data is set as a second logic bit, the access operation is performed in response to the access command sent from the flash memory controller.

7. The flash memory controller of claim 1 , wherein the feature information comprises another parameter data; when the another parameter data is set as a first logic bit, the access operation, to be performed by the flash memory device, is configured to change address information of at least one data unit for the first plane; and, when the another parameter data is set as a second logic bit, the access operation, to be performed by the flash memory device, is configured to not change the address information of the at least one data unit for the first plane.

8. A method of a flash memory controller to be used in a storage device and coupled to a flash memory device of the storage device through a specific communication interface, comprising:

providing an input/output (I/O) circuit coupled to the flash memory device through the specific communication interface and used for sending commands and data between the flash memory device and a processor; and

using the processor to control the I/O circuit sending a set-feature signal to the flash memory device to enable, disable, or configure an access operation of the flash memory device, to make the flash memory device perform the access operation to control the flash memory device generating second address information associated with a second plane of the flash memory device according to a first address information of a first plane of the flash memory device, and then selecting multiple data units at the first plane and the second plane based on the first address information and the second address information in response to an access command or a specific indication command so as to perform the access operation upon the multiple data units at the first plane and the second plane;

wherein the set-feature signal comprises a set-feature command and a feature information which is associated with the access operation; the access operation is a copy back read operation, an erase operation, or a write operation; the feature information comprises a parameter data; when the parameter data is set as a first logic bit, the access operation, to be performed by the flash memory device, is enabled and configured as a sequential mode which is arranged to sequentially access data units of the different planes of the flash memory device according to serial numbers of the different planes in response to the access command or the specific indication command sent from the flash memory controller.

9. The method of claim 8 , further comprising:

sending the set-feature signal to the flash memory device to enable, disable, or configure the access operation of the flash memory device when the flash memory controller is powered on or the flash memory device is powered on.

10. The method of claim 6 , wherein when the parameter data is set as a second logic bit, the access operation of the flash memory device is disabled.

11. The method of claim 8 , wherein the feature information comprises another parameter data; when the another parameter data is set as a first logic bit, the access operation, to be performed by the flash memory device, is configured to be performed according to a bit map information which is calculated and stored by the flash memory device.

12. The method of claim 11 , wherein when the another parameter data is set as a second logic bit, the access operation of the flash memory device is performed according to an updated bit map information sent from the flash memory controller.

13. The method of claim 8 , wherein the feature information comprises another parameter data; when the another parameter data is set as a first logic bit, the access operation, to be performed by the flash memory device, is configured to be performed in response to the specific indication sent from the flash memory controller; and, when the another parameter data is set as a second logic bit, the access operation is performed in response to the access command sent from the flash memory controller.

14. The method of claim 8 , wherein the feature information comprises another parameter data; when the another parameter data is set as a first logic bit, the access operation, to be performed by the flash memory device, is configured to change address information of at least one data unit for the first plane; and, when the another parameter data is set as a second logic bit, the access operation, to be performed by the flash memory device, is configured to not change the address information of the at least one data unit for the first plane.