Circuit device and electronic apparatus
View Patent ↗A circuit device includes a bus, a plurality of master circuits that are coupled to the bus and are bus masters in the bus, and a plurality of slave circuits that are coupled to the plurality of master circuits via the bus and are bus slaves in the bus. Access authority to the bus slaves is set for the plurality of master circuits, and permission setting of read access or write access from the bus masters is performed for the plurality of slave circuits. The plurality of master circuits determine whether the plurality of slave circuits are accessible based on the access authority and the permission setting.
1. A circuit device comprising:
a bus;
a plurality of master circuits that are coupled to the bus and are bus masters in the bus; and
a plurality of slave circuits that are coupled to the plurality of master circuits via the bus and are bus slaves in the bus, wherein
access authority to the bus slaves is set for the plurality of master circuits,
permission setting of read access or write access from the bus masters is performed for the plurality of slave circuits, and
the plurality of master circuits determine whether the plurality of slave circuits are accessible based on the access authority and the permission setting.
2. The circuit device according to claim 1 , wherein
the plurality of master circuits include a first master circuit for which the access authority to the bus slaves is set and a second master circuit for which no access authority to the bus slaves is set,
the plurality of slave circuits include a first slave circuit for which first permission setting is performed,
the first master circuit is permitted to perform the read access or the write access to the first slave circuit without depending on the first permission setting, and
the second master circuit is permitted to perform the read access or the write access to the first slave circuit based on the first permission setting.
3. The circuit device according to claim 2 , wherein
the first master circuit is a processor or a DMA controller.
4. The circuit device according to claim 2 , wherein
the second master circuit is an external bus interface or a debug circuit.
5. The circuit device according to claim 1 , further comprising:
a nonvolatile memory configured to store protection setting information that is information on the access authority and the permission setting.
6. The circuit device according to claim 5 , further comprising:
a memory controller configured to perform access authority setting and the permission setting based on the protection setting information read from the nonvolatile memory.
7. The circuit device according to claim 6 , wherein
the memory controller performs the permission setting for the plurality of slave circuits using a first signal line provided separately from the bus.
8. The circuit device according to claim 6 , wherein
the memory controller performs the access authority setting for the plurality of master circuits using a second signal line provided separately from the bus.
9. The circuit device according to claim 1 , further comprising:
an authority control circuit provided between the plurality of master circuits and the bus, wherein
the authority control circuit sets the access authority by rewriting information on the access authority included in bus access information from the plurality of master circuits.
10. The circuit device according to claim 9 , further comprising:
a nonvolatile memory configured to store protection setting information that is information on the access authority and the permission setting; and
a memory controller configured to control the nonvolatile memory, wherein
the memory controller sets the access authority to the authority control circuit.
11. The circuit device according to claim 6 , wherein
the memory controller permits writing of the protection setting information to the nonvolatile memory when a setting storage area of the protection setting information is completely erased.
12. The circuit device according to claim 11 , wherein
the memory controller does not permit partial erasure of the setting storage area when the protection setting information is stored in the setting storage area.
13. The circuit device according to claim 1 , wherein
information on the permission setting is written to a register provided in each of the plurality of slave circuits.
14. The circuit device according to claim 1 , wherein
information on the access authority is included in bus access information on the bus.
15. The circuit device according to claim 1 , further comprising:
a bus bridge circuit provided between the bus and a peripheral bus to which a plurality of peripheral circuits are coupled, wherein
information on the permission setting for each of the plurality of peripheral circuits is written in a register provided in the bus bridge circuit.
16. An electronic apparatus comprising:
the circuit device according to claim 1 .