Power management circuit including on-board current sensing across inductor and on-die current limit detection circuit

1. An apparatus, comprising:

an integrated circuit (IC), comprising:

one or more cores; and

a current limit detection circuit;

a voltage regulator;

an inductor coupled between the voltage regulator and the one or more cores of the IC; and

a current sensing circuit including inputs coupled across the inductor and an output coupled to the current limit detection circuit of the IC, wherein the current sensing circuit comprises a resistor coupled in series with a capacitor, wherein the resistor and the capacitor are coupled in parallel with the inductor;

wherein the current limit detection circuit comprises:

an analog front-end including inputs coupled across the capacitor;

an analog-to-digital converter (ADC) including an input coupled to an output of the analog front-end;

a static current detector including an input coupled to the output of the analog front-end;

a static offset correction circuit including a first input coupled to an output of the static current detector, and a second input coupled to an output of the ADC;

a digital adder including a first input coupled to the output of the ADC, and a second input coupled to an output of the static offset correction circuit; and

a current limit violation detection circuit including an input coupled to an output of the digital adder.

2. The apparatus of claim 1 , wherein the analog front-end comprises an instrumentation amplifier or a differential amplifier.

3. The apparatus of claim 1 , wherein the IC further comprises a current reduction control circuit including an input coupled to an output of the current limit violation detection circuit and an output coupled to the one or more cores.

4. The apparatus of claim 1 , wherein the current limit detection circuit further comprises:

a transient current detector including an input coupled to the output of the analog front-end; and

a transient offset correction circuit including a first input coupled to an output of the transient current detector and a second input coupled to the output of the ADC;

wherein the digital adder includes a third input coupled to an output of the transient offset correction circuit.

5. The apparatus of claim 4 , wherein the IC further comprises a current reduction control circuit including an input coupled to an output of the current limit violation detection circuit and an output coupled to the one or more cores.

6. The apparatus of claim 1 , wherein the current sensing circuit further comprises a resistive device coupled in parallel with the capacitor.

7. The apparatus of claim 6 , wherein the resistive device has a temperature coefficient substantially equal in magnitude and opposite in sign as a temperature coefficient of an intrinsic resistance of the inductor.

8. The apparatus of claim 1 , wherein the voltage regulator includes a temperature signal output coupled to the current limit detection circuit of the IC.

9. The apparatus of claim 8 , wherein the current limit detection circuit further comprises

a temperature offset correction circuit including an input coupled to the temperature signal output of the voltage regulator;

wherein the digital adder includes a third input coupled to an output of the temperature offset correction circuit.

10. The apparatus of claim 9 , wherein the IC further comprises a current reduction control circuit including an input coupled to an output of the current limit violation detection circuit and an output coupled to the one or more cores.

11. The apparatus of claim 1 , further comprising:

a set of voltage regulators including the voltage regulator;

a set of inductors including the inductor, wherein the set of inductors are coupled between the set of voltage regulators and the one or more cores of the IC, respectively; and

a set of current sensing circuits including a set of inputs coupled across the set of inductors, respectively, wherein the set of current sensing circuits includes a set of outputs coupled to the current limit detection circuit of the IC.

12. The apparatus of claim 11 , wherein the current limit detection circuit comprises

a voltage summer including inputs coupled to the set of outputs of the set of current sensing circuits;

wherein the inputs of the analog front-end are coupled to an output of the voltage summer.

13. The apparatus of claim 12 , wherein the IC further comprises a current reduction control circuit including an input coupled to an output of the current limit violation detection circuit and an output coupled to the one or more cores.

14. The apparatus of claim 1 , further comprising:

a set of voltage regulators including the voltage regulator;

a set of inductors including the inductor, wherein the set of inductors are coupled between the set of voltage regulators and the one or more cores of the IC, respectively; and

at least one current sensing circuit including inputs coupled across at least one of the set of inductors, respectively, wherein the at least one current sensing circuit includes at least one output coupled to the current limit detection circuit of the IC.

15. The apparatus of claim 14 , wherein:

the inputs of the analog front-end are coupled to the at least one output of the at least one current sensing circuit, respectively;

the current limit detection circuit further comprises a multiplier including a first input coupled to an output of the ADC, and a second input configured to receive a multiplication factor; and

the current limit violation detection circuit includes an input coupled to an output of the multiplier.

16. The apparatus of claim 1 , wherein the IC is implemented as a system on chip (SOC) including the one or more cores and the current limit detection circuit, wherein the SOC is mounted on a printed circuit board (PCB), and wherein the voltage regulator, inductor, and current sensing circuit are off-chip components mounted on the PCB.

17. A method, comprising:

sensing a first voltage across an inductor coupled between a voltage regulator and one or more cores of an integrated circuit (IC), wherein sensing the first voltage across the inductor comprises generating a second voltage across a capacitor coupled in series with a resistor, wherein the capacitor and the resistor are coupled in parallel with the inductor;

providing the first voltage to the IC; and

controlling a current flowing through the inductor and to the one or more cores of the IC based on the first voltage, wherein controlling the current comprises:

amplifying the second voltage to generate a current-related voltage;

converting the current-related voltage to a current-related digital signal;

correcting the current-related digital signal for tolerance variation associated with at least one of an intrinsic resistance of the inductor, an intrinsic inductance of the inductor, a resistance of the resistor, and a capacitance of the capacitor;

comparing the corrected current-related digital signal to one or more current limits; and

reducing the current flowing to the one or more cores based on the comparison.

18. The method of claim 17 , wherein generating the second voltage across the capacitor comprises setting a first time constant associated with the resistor and capacitor to be substantially the same as a second time constant associated with the inductor.

19. The method of claim 17 , further comprising compensating the second voltage for variation of an intrinsic resistance of the inductor with temperature.

20. The method of claim 17 , wherein controlling the current further comprises

correcting the current-related digital signal for variation of at least one of the intrinsic resistance of the inductor, the intrinsic inductance of the inductor, the resistance of a resistor, and the capacitance of a capacitor with temperature.

21. An apparatus, comprising:

means for sensing a first voltage across an inductor coupled between a voltage regulator and one or more cores of an integrated circuit (IC), wherein the means for sensing the first voltage across the inductor comprises means for generating a second voltage across a capacitor coupled in series with a resistor, the capacitor and resistor being coupled in parallel with the inductor;

means for providing the first voltage to the IC; and

means for controlling a current flowing through the inductor and to the one or more cores of the IC based on the first voltage, wherein the means for controlling the current comprises:

means for amplifying the second voltage to generate a current-related voltage;

means for converting the current-related voltage to a current-related digital signal;

means for correcting the current-related digital signal for tolerance variation associated with at least one of an intrinsic resistance of the inductor, an intrinsic inductance of the inductor, a resistance of the resistor, and a capacitance of the capacitor;

means for comparing the corrected current-related digital signal to one or more current limits; and

means for reducing the current flowing to the one or more cores based on the comparison.

22. An apparatus, comprising:

an integrated circuit (IC), comprising:

one or more cores; and

a current limit detection circuit;

a voltage regulator;

an inductor coupled between the voltage regulator and the one or more cores of the IC; and

a current sensing circuit including inputs coupled across the inductor and an output coupled to the current limit detection circuit of the IC, wherein the current sensing circuit comprises a resistor coupled in series with a capacitor, wherein the resistor and the capacitor are coupled in parallel with the inductor;

wherein the current limit detection circuit comprises:

an analog front-end including inputs coupled across the capacitor;

an analog-to-digital converter (ADC) including an input coupled to an output of the analog front-end;

a transient current detector including an input coupled to the output of the analog front-end;

a transient offset correction circuit including a first input coupled to an output of the transient current detector and a second input coupled to an output of the ADC;

a digital adder including a first input coupled to the output of the ADC, a second input coupled to an output of the transient offset correction circuit; and

a current limit violation detection circuit including an input coupled to an output of the digital adder.

23. The apparatus of claim 22 , wherein the IC further comprises a current reduction control circuit including an input coupled to an output of the current limit violation detection circuit and an output coupled to the one or more cores.