Hardware and protocols to support image transfers over MIPI I2C/I3C buses
In one embodiment, a system includes a host system-on-chip (SoC) comprising vision processing circuitry and a camera connected to the host SoC through an Inter-Integrated Circuit (I3C) bus. The camera includes circuitry to generate image data and transmit an interrupt signal to the host SoC over the I3C bus indicating the image data is ready for transfer. The host SoC vision processing circuitry is to transmit a read message to the camera over the I3C bus based on the interrupt signal and receive a set of line payload packets including the image data over the I3C bus based on the read message.
1 . An apparatus comprising:
controller circuitry to interface with a camera over an Inter-Integrated Circuit (I3C) bus; and
frame processing circuitry to:
obtain a signal from the camera over the I3C bus, the signal to indicate image data is ready for transfer;
cause a first message to be transmitted to the camera over the I3C bus after receipt of the signal, the first message including a private common command code (CCC) and a first value, the first value to indicate the camera is to provide an image frame header;
cause a second message to be transmitted to the camera over the I3C bus after receipt of the image frame header, the second message including the private CCC and a second value different from the first value, the second value to indicate the camera is to provide image payload data; and
process a set of one or more line payload packets over the I3C bus after transmission of the second message, the set of line payload packets including the image payload data from the camera.
2 . The apparatus of claim 1 , wherein the signal is an In-Band Interrupt (IBI) signal.
3 . The apparatus of claim 1 , wherein the private CCC is 0xC0, the second value is a defining byte code of 0x01, and the second message includes an address of the camera on the I3C bus.
4 . The apparatus of claim 1 , wherein the private CCC is 0xC0, the first value is a defining byte code of 0x04, and the first message includes an address of the camera on the I3C bus.
5 . The apparatus of claim 1 , wherein the second message is one or a plurality of second messages, and the frame processing circuitry is to cause respective ones of the second message to be transmitted before receipt of corresponding ones of the line payload packets.
6 . The apparatus of claim 1 , wherein the frame processing circuitry is to cause the second message to be transmitted before receipt of a plurality of the line payload packets.
7 . The apparatus of claim 1 , wherein the frame processing circuitry is to verify the image payload data based on a cyclic redundancy check (CRC) value received over the I3C bus.
8 . The apparatus of claim 1 , wherein the frame processing circuitry is to, while the line payload packets are processed, cause a drop frame message to be transmitted to the camera over the I3C bus.
9 . The apparatus of claim 8 , wherein the private CCC is a first private CCC, and the drop frame message includes a second the private CCC of 0xC0, a defining byte code of 0x02, and an address of the camera on the I3C bus.
10 . The apparatus of claim 1 , wherein the frame processing circuitry is to cause a frame demand message to be transmitted to the camera over the I3C bus before receipt of the signal.
11 . The apparatus of claim 1 , including controller circuitry to interface with the camera over a Camera Serial Interface 2 (CSI-2) bus.
12 . The apparatus of claim 11 , including:
first image processing circuitry to obtain first image data from the camera over the I3C bus and the CSI-2 bus; and
second image processing circuitry to obtain second image data from the camera over the I3C bus.
13 . A method comprising:
receiving, at a system-on-chip (SoC) of a computing device, a signal from a camera over an Inter-Integrated Circuit (I3C) bus, the signal indicating image data is ready for transfer;
transmitting a first message to the camera over the I3C bus after receipt of the signal, the first message including a private common command code (CCC) and a first value, the first value to indicate the camera is to provide an image frame header;
transmitting a second message to the camera over the I3C bus after receipt of the image frame header, the second message including the private CCC and a second value different from the first value, the second value to indicate the camera is to provide image payload data;
receiving one or more line payload packets over the I3C bus after transmission of the second message, the one or more line payload packets including the image payload data from the camera;
generating image pixel interface (IPI) data based on the line payload packets; and
processing the IPI data at the SoC.
14 . The method of claim 13 , including:
receiving a cyclic redundancy check (CRC) value from the camera over the I3C bus after the one or more line payload packets; and
verifying the image payload data based on the CRC value.
15 . The method of claim 13 , including transmitting a frame demand message to the camera over the I3C bus before receipt of the signal.
16 . A system comprising:
a host system-on-chip (SoC) including vision processing circuitry; and
a camera connected to the host SoC through an Inter-Integrated Circuit (I3C) bus, the camera including first circuitry to generate image data and transmit an interrupt signal to the host SoC over the I3C bus, the interrupt signal to indicate the image data is ready for transfer;
wherein the host SoC vision processing circuitry is to:
cause transmission of a first message to the camera over the I3C bus after receipt of the interrupt signal, the first message including a private common command code (CCC) and a first value, the first value to indicate the camera is to provide an image frame header;
cause a second message to be transmitted to the camera over the I3C bus after receipt of the image frame header, the second message including the private CCC and a second value different from the first value, the second value to indicate the camera is to provide image payload data; and
cause receipt of a set of one or more line payload packets over the I3C bus after the transmission of the second message, the set of line payload packets including the image payload data.
17 . The system of claim 16 , wherein the host SoC vision processing circuitry is to verify the image payload data based on a cyclic redundancy check (CRC) value from the I3C bus.
18 . The system of claim 16 , wherein the host SoC includes second circuitry to obtain second image data from the camera over a Camera Serial Interface 2 (CSI-2) bus.
19 . The system of claim 16 , wherein the system includes a laptop computer system, the host SoC is in a base of the laptop computer system and the camera is in a lid of the laptop computer system.
20 . The apparatus of claim 10 , wherein the frame demand message includes the private CCC, a third value to define the frame demand message, and an address of the camera on the I3C bus, the third value different from the first value and the second value.
21 . The method of claim 15 , wherein the frame demand message includes the private CCC, a third value to define the frame demand message, and an address of the camera on the I3C bus, the third value different from the first value and the second value.
22 . The system of claim 16 , wherein the host SoC vision processing circuitry is to cause a frame demand message to be transmitted to the camera over the I3C bus before receipt of the interrupt signal, the frame demand message including the private CCC, a third value to define the frame demand message, and an address of the camera on the I3C bus, the third value different from the first value and the second value.