IP Library › Granted Patent US 11,822,813
Granted Patent B2
US 11,822,813 · App. 17/680,773 · Granted Nov 21, 2023

Storage device, operation method of storage device, and storage system using the same

Inventors: Wonseb Jeong (Suwon-si, KR); Yang Seok Ki (San Jose, CA); Jungmin Seo (Seongnam-si, KR); Beomkyu Shin (Seongnam-si, KR); Sangoak Woo (Anyang-si, KR); Younggeon Yoo (Seoul, KR); Chanho Yoon (Seoul, KR); Myungjune Jung (Suwon-si, KR)
G06F3/0655G06F3/0604G06F3/0679G06F12/0802G06F2212/60
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Quick Facts
Patent No.
US 11,822,813
App. No.
17/680,773
Granted
Nov 21, 2023
Kind
B2
Abstract

A storage device includes a nonvolatile memory device and a storage controller. The storage controller includes a multi-protocol host interface circuit that receives a first-type request including a first logical address from an external host and transmits/receives data corresponding to the first-type request with the external host by a block unit. Additionally, the multi-protocol host interface circuit receives a second-type request including a first physical address from the external host and transmits/receives data corresponding to the second-type request with the external host by a unit smaller than the block unit. A mapping cache manager manages an address translation table cache, sends an address translation request including the first physical address to the external host, and receives a response including mapping information corresponding to the first physical address from the external host.

Claims (75)

1. A storage device comprising:

a nonvolatile memory device; and

a storage controller, wherein the storage controller includes:

a multi-protocol host interface circuit configured to:

receive a first-type request including a first logical address from an external host,

transmit/receive data corresponding to the first-type request to/from the external host by a block unit,

receive a second-type request including a first physical address from the external host, and

transmit/receive data corresponding to the second-type request to/from the external host by a unit smaller than the block unit; and

a mapping cache manager configured to:

manage an address translation table cache,

send an address translation request including the first physical address to the external host, and

receive a response including mapping information corresponding to the first physical address from the external host.

2. The storage device of claim 1 , wherein the mapping cache manager:

caches a portion of mapping information between a logical address and a physical address managed by the external host,

stores, in response to the response, a second logical address in the address translation table cache that is correlated with the first physical address, and

translates the first physical address into the second logical address based on the address translation table cache.

3. The storage device of claim 2 , further comprising a flash translation layer configured to translate the first logical address into a first physical page address in response to the first-type request and to translate the second logical address received from the mapping cache manager into a second physical page address in response to the second-type request.

4. The storage device of claim 2 , wherein the mapping cache manager receives an address invalidation request including the first physical address from the external host and invalidates mapping information of the first physical address in the address translation table cache in response to the address invalidation request.

5. The storage device of claim 1 , further comprising a request scheduler configured to schedule the first-type request and the second-type request.

6. The storage device of claim 5 , wherein under control of the request scheduler and when the second-type request is received after the first-type request is received, an input/output command corresponding to the second-type request is transferred to the nonvolatile memory device and then an input/output command corresponding to the first-type request is transferred to the nonvolatile memory device.

7. The storage device of claim 5 , wherein under control of the request scheduler and after the first-type request is received, the second-type request is received and then a command corresponding to the first-type request is transferred to the nonvolatile memory device, a suspend command corresponding to the first-type request is transferred to the nonvolatile memory device, an input/output command corresponding to the second-type request is transferred to the nonvolatile memory device, and a resume command corresponding to the first-type request is transferred to the nonvolatile memory device.

8. The storage device of claim 5 , wherein:

the request scheduler schedules the first-type request and the second-type request based on arbitration information received from the external host and current status information, and

the current status information includes status information of current input/output requests, QoS configuration information, and information about a ratio of a cache miss and a cache hit of the address translation table cache.

9. The storage device of claim 1 , wherein the first-type request corresponds to an NVMe (Non-Volatile Memory express) protocol and the second-type request corresponds to a CXL (Compute eXpress Link) protocol.

10. An operation method of a storage device which includes a nonvolatile memory device and a storage controller, the method comprising:

receiving a first-type request including a first logical address and first data size information of a first unit, which is a block unit, from an external host;

performing an operation corresponding to the first-type request on the nonvolatile memory device;

receiving a second-type request including a first physical address and second data size information of a second unit smaller than the first unit from an external host;

sending an address translation request including the first physical address to the external host in response to the second-type request;

receiving a response including a second logical address corresponding to the first physical address from the external host; and

performing an operation corresponding to the second-type request on the nonvolatile memory device, based on the response including the second logical address.

11. The method of claim 10 , wherein the performing of the operation corresponding to the first-type request on the nonvolatile memory device includes:

translating, by the storage controller, the first logical address into a first physical page address based on a mapping table; and

sending, by the storage controller, an input/output command including the first physical page address and corresponding to the first-type request to the nonvolatile memory device.

12. The method of claim 10 , wherein the performing of the operation corresponding to the second-type request on the nonvolatile memory device based on the response including the second logical address includes:

storing, by the storage controller, the second logical address in an address translation table cache to be correlated with the first physical address;

translating, by the storage controller, the first physical address into the second logical address based on the address translation table cache;

translating, by the storage controller, the second logical address into a second physical page address based on the mapping table; and

sending, by the storage controller, an input/output command including the second physical page address and corresponding to the second-type request to the nonvolatile memory device.

13. The method of claim 10 , the method further comprising:

receiving, by the storage controller, another second-type request including a second physical address and third data size information of the second unit from the external host;

determining, by the storage controller and in response to the other second-type request, whether mapping information about the second physical address is present in an address translation table cache;

when the mapping information about the second physical address is present, translating by the storage controller the second physical address into a third logical address based on the address translation table cache;

translating, by the storage controller, the third logical address into a third physical page address based on a mapping table; and

sending, by the storage controller, an input/output command including the third physical page address and corresponding to the other second-type request to the nonvolatile memory device.

14. The method of claim 10 , further comprising:

receiving an address invalidation request including the first physical address from the external host;

invalidating mapping information of the first physical address in an address translation table cache in response to the address invalidation request; and

sending a response corresponding to the address invalidation request to the external host.

15. The method of claim 10 , further comprising scheduling the first-type request and the second-type request.

16. The method of claim 10 , further comprising:

receiving arbitration information from the external host;

setting an arbitration scheme and a parameter based on the arbitration information; and

scheduling the first-type request and the second-type request based on the arbitration scheme and the parameter.

17. The method of claim 16 , further comprising:

determining whether a condition of needing to change the parameter is satisfied; and

when the condition is satisfied, changing a value of the parameter based on current status information and the arbitration information, wherein

the current status information includes status information of current input/output requests, QoS configuration information, and information about a ratio of a cache miss and a cache hit of an address translation table cache.

18. A storage system comprising:

a host configured to:

send a first-type request including a first logical address,

send a second-type request including a first physical address, and

manage mapping information between a logical address and a physical address; and

a storage device configured to:

receive the first-type request and the second-type request from the host,

cache a portion of the mapping information to manage an address mapping table cache,

provide a data access of a block unit in response to the first-type request, and

provide a data access of a unit smaller than the block unit in response to the second-type request.

19. The storage system of claim 18 , wherein:

the storage device sends an address translation request for a first physical address to the host, and

in response to the address translation request, the host translates the first physical address into a second logical address based on the mapping information and sends a response including the second logical address to the storage device.

20. The storage system of claim 18 , wherein:

when mapping information about the first physical address is updated, the host sends an invalidation request for the first physical address to the storage device, and

the storage device invalidates mapping information about the first physical address in response to the invalidation request.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 25, 2022
From: JEONG, WONSEB; KI, YANG SEOK; SEO, JUNGMIN; SHIN, BEOMKYU; WOO, SANGOAK; YOO, YOUNGGEON; YOON, CHANHO; JUNG, MYUNGJUNE
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 059108/0697 →
Priority Claims (1)
KR 10-2022-0010998 · Jan 25, 2022 · national
Continuity (2)
Provisional Application 63294251 · Dec 28, 2021
Related Publication 20230205449A1 · Jun 29, 2023
Cited By (1)
US 12,561,245