Microelectronic packages having a die stack and a device within the footprint of the die stack
A microelectronic package may be fabricated having a microelectronic die stack attached to a microelectronic substrate and at least one microelectronic device, which is separate from the microelectronic die stack, attached to the microelectronic substrate within the footprint of one of the microelectronic dice within the microelectronic die stack. In one embodiment, the microelectronic die stack may have a plurality of stacked microelectronic dice, wherein one microelectronic die of the plurality of microelectronic dice has a footprint greater than the other microelectronic die of the plurality of microelectronic dice, and wherein the at least one microelectronic device is attached to the one microelectronic die of the plurality of microelectronic dice having the greater footprint.
1. A microelectronic package, comprising:
a microelectronic substrate having a first surface;
a microelectronic die stack electrically attached to the first surface of the microelectronic substrate first surface, wherein the microelectronic die stack comprises a first microelectronic die attached to the first surface of the microelectronic substrate, a second microelectronic die stacked on the first microelectronic die, and a third microelectronic die stacked on the second microelectronic die, wherein a footprint of the first microelectronic die is within a footprint of the second microelectronic die, wherein the footprint of the second microelectronic die is within a footprint of the third microelectronic; and
at least one microelectronic device electrically attached to the first surface of the microelectronic substrate, wherein the at least one microelectronic device is within the footprint of the third microelectronic die, and wherein the at least one microelectronic device is outside the footprint of the first microelectronic die and outside the footprint of the second microelectronic die.
2. The microelectronic package of claim 1 , wherein the footprint of the second microelectronic die is larger than the footprint of the first microelectronic die.
3. The microelectronic package of claim 1 , further comprising at least one bond wire electrically connecting the microelectronic die stack to the microelectronic substrate first surface.
4. The microelectronic package of claim 1 , wherein the first microelectronic die is electrically attached to the microelectronic substrate first surface by interconnects extending between substrate bond pads on the microelectronic substrate first surface and mirror-image bond pads on the first microelectronic die.
5. The microelectronic package of claim 1 , further comprising a die attach film, wherein the die attach film abuts the second microelectronic die and the third microelectronic die, and wherein the die attach film extends beyond the footprint of the second microelectronic die.
6. The microelectronic package of claim 1 , wherein the first microelectronic die comprises an application specific integrated circuit device, wherein the second microelectronic die comprises a volatile memory device, and wherein the third microelectronic die comprises a non-volatile memory device.
7. A method of fabricating a microelectronic package, comprising:
forming a microelectronic substrate having a first surface;
electrically attaching at least one microelectronic device to the microelectronic substrate first surface;
electrically attaching a first microelectronic die to the microelectronic substrate first surface;
stacking a second microelectronic die on the first microelectronic die;
stacking a third microelectronic die on the second microelectronic die, wherein a footprint of the first microelectronic die is within a footprint of the second microelectronic die, wherein the footprint of the second microelectronic die is within a footprint of the third microelectronic, wherein the at least one microelectronic device is within the footprint of the third microelectronic die, and wherein the at least one microelectronic device is outside the footprint of the first microelectronic die and outside the footprint of the second microelectronic die.
8. The method of claim 7 , wherein the footprint of the second microelectronic die is larger than the footprint of the first microelectronic die.
9. The method of claim 7 , further comprising electrically connecting the microelectronic die stack to the first surface of the microelectronic substrate with at least one bond wire.
10. The method of claim 7 , wherein electrically attaching the first microelectronic die to the microelectronic substrate first surface comprises electrically attaching the first microelectronic die to the microelectronic substrate first surface by attaching interconnects extending between substrate bond pads on the microelectronic substrate first surface and mirror-image bond pads on the first microelectronic die.
11. The method of claim 7 , further comprising forming a die attach film to abut the second microelectronic die and the third microelectronic die, and wherein the die attach film extends beyond the footprint of the second microelectronic die.
12. The method of claim 7 , wherein the first microelectronic die comprises an application specific integrated circuit device, wherein the second microelectronic die comprises a volatile memory device, and wherein the third microelectronic die comprises a non-volatile memory.
13. An electronic system, comprising:
a board; and
a microelectronic package attached to the board, wherein the microelectronic package comprises:
a microelectronic substrate having a first surface;
a microelectronic die stack electrically attached to the first surface of the microelectronic substrate first surface, wherein the microelectronic die stack comprises a first microelectronic die attached to the first surface of the microelectronic substrate, a second microelectronic die stacked on the first microelectronic die, and a third microelectronic die stacked on the second microelectronic die, wherein a footprint of the first microelectronic die is within a footprint of the second microelectronic die, wherein the footprint of the second microelectronic die is within a footprint of the third microelectronic; and
at least one microelectronic device electrically attached to the first surface of the microelectronic substrate, wherein the at least one microelectronic device is within the footprint of the third microelectronic die, and wherein the at least one microelectronic device is outside the footprint of the first microelectronic die and outside the footprint of the second microelectronic die.
14. The electronic system of claim 13 , wherein the footprint of the second microelectronic die is larger than the footprint of the first microelectronic die.
15. The electronic system of claim 13 , further comprising at least one bond wire electrically connecting the microelectronic die stack to the microelectronic substrate first surface.
16. The electronic system of claim 13 , wherein the first microelectronic die is electrically attached to the microelectronic substrate first surface by interconnects extending between substrate bond pads on the microelectronic substrate first surface and mirror-image bond pads on the first microelectronic die.
17. The electronic system of claim 13 , further comprising a die attach film, wherein the die attach film abuts the second microelectronic die and the third microelectronic die, and wherein the die attach film extends beyond the footprint of the second microelectronic die.
18. The electronic system of claim 13 , wherein the first microelectronic die comprises an application specific integrated circuit device, wherein the second microelectronic die comprises a volatile memory device, and wherein the third microelectronic die comprises a non-volatile memory device.