IP Library › Granted Patent US 11,558,568
Granted Patent B2
US 11,558,568 · App. 17/683,018 · Granted Jan 17, 2023

Image sensor and imaging device

Inventors: Naoki Kawazu (Kanagawa, JP); Motonobu Torii (Fukuoka, JP); Motohashi Yuichi (Tokyo, JP); Atsushi Suzuki (Kanagawa, JP); Junichiro Azami (Kanagawa, JP)
Assignee: Sony Semiconductor Solutions Corporation
H04N5/367H04N5/37213H04N17/002
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Quick Facts
Patent No.
US 11,558,568
App. No.
17/683,018
Granted
Jan 17, 2023
Kind
B2
Abstract

An imaging device having first and second pixels is described. The first pixel includes a first transfer transistor, a first reset transistor, a first amplifier transistor and a first select transistor. The second pixel includes a first photoelectric conversion element, a second transfer transistor, a second reset transistor, a second amplifier transistor and a second select transistor.

Claims (44)

1. An imaging device comprising:

a pixel including:

a first photoelectric conversion element;

a first transfer transistor, wherein a first terminal of the first transfer transistor is coupled to the first photoelectric conversion element;

a first amplifier transistor, wherein a gate of the first amplifier transistor is coupled to a second terminal of the first transfer transistor and wherein a first terminal of the first amplifier transistor is coupled to a power line; and

a first reset transistor, wherein a first terminal of the first reset transistor is coupled to the second terminal of the first transfer transistor and wherein a second terminal of the first reset transistor is coupled to the power line;

a test signal generator including:

a second transfer transistor having a first terminal and a second terminal;

a second amplifier transistor, wherein a gate of the second amplifier transistor is coupled to the second terminal of the second transfer transistor and wherein a first terminal of the second amplifier transistor is coupled to the power line; and

a second reset transistor, wherein a first terminal of the second reset transistor is coupled to the second terminal of the second transfer transistor and wherein a second terminal of the second reset transistor is coupled to a test voltage generation circuit which is separated from the power line;

a reset control signal line coupled to a gate of the first reset transistor in the pixel and a gate of the second reset transistor in the test signal generator;

a vertical scanning unit coupled to the reset control signal line.

2. The imaging device according to claim 1 , wherein the second terminal of the second reset transistor is not coupled to the power line.

3. The imaging device according to claim 1 , wherein the first terminal of the second transfer transistor is coupled to the test voltage generation circuit.

4. The imaging device according to claim 1 , wherein the test signal generator does not include a photoelectric conversion element.

5. The imaging device according to claim 1 , wherein a pixel region including the pixel is disposed between first and second test signal generator regions including the test signal generator in a pixel array.

6. The imaging device according to claim 1 , wherein the vertical scanning unit is configured to generate a reset control signal and output the reset control signal through the reset control signal line.

7. The imaging device according to claim 1 , further comprising a failure detector coupled to a second terminal of the second amplifier transistor via a second select transistor and an analog-to-digital conversion element, wherein the failure detector comprises at least one comparison element.

8. The imaging device according to claim 7 , wherein the failure detector is configured to detect a failure of the reset control signal line.

9. The imaging device according to claim 1 , wherein the imaging device is mounted on a vehicle.

10. An imaging device comprising:

a first chip including:

a pixel including:

a first photoelectric conversion element;

a first transfer transistor, wherein a first terminal of the first transfer transistor is coupled to the first photoelectric conversion element;

a first amplifier transistor, wherein a gate of the first amplifier transistor is coupled to a second terminal of the first transfer transistor and wherein a first terminal of the first amplifier transistor is coupled to a power line; and

a first reset transistor, wherein a first terminal of the first reset transistor is coupled to the second terminal of the first transfer transistor and wherein a second terminal of the first reset transistor is coupled to the power line;

a test signal generator including:

a second transfer transistor having a first terminal and a second terminal;

a second amplifier transistor, wherein a gate of the second amplifier transistor is coupled to the second terminal of the second transfer transistor and wherein a first terminal of the second amplifier transistor is coupled to the power line; and

a second reset transistor, wherein a first terminal of the second reset transistor is coupled to the second terminal of the second transfer transistor and wherein a second terminal of the second reset transistor is coupled to a test voltage generation circuit which is separated from the power line; and

a reset control signal line coupled to the pixel and the test signal generator; and

a second chip including:

a vertical scanning unit coupled to the reset control signal line via a first inter-chip connection terminal.

11. The imaging device according to claim 10 , wherein the second terminal of the second reset transistor is not coupled to the power line.

12. The imaging device according to claim 10 , wherein the first terminal of the second transfer transistor is coupled to the test voltage generation circuit.

13. The imaging device according to claim 10 , wherein the test signal generator does not include a photoelectric conversion element.

14. The imaging device according to claim 10 , wherein a pixel region including the pixel is disposed between first and second test signal generator regions including the test signal generator in a pixel array.

15. The imaging device according to claim 10 , wherein the vertical scanning unit is configured to generate a reset control signal and output the reset control signal through the reset control signal line.

16. The imaging device according to claim 10 , further comprising a failure detector coupled to a second terminal of the second amplifier transistor via a second select transistor and an analog-to-digital conversion element, wherein the failure detector comprises at least one comparison element.

17. The imaging device according to claim 16 , wherein the failure detector is configured to detect a failure of the reset control signal line.

18. The imaging device according to claim 10 , wherein the imaging device is mounted on a vehicle.

19. The imaging device according to claim 10 , wherein the first transfer transistor has a gate configured to receive a transfer enabling signal on a transfer control signal line.

20. The imaging device according to claim 19 , wherein the gate of the first amplifier transistor is configured to receive a signal from the first transfer transistor based on an electric charge generated by the first photoelectric conversion element.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 2, 2022
From: KAWAZU, NAOKI; TORII, MOTONOBU; YUICHI, MOTOHASHI; SUZUKI, ATSUSHI; AZAMI, JUNICHIRO
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 060084/0842 →
Priority Claims (1)
JP JP2016-233875 · Dec 1, 2016 · national
Continuity (3)
Continuation 17197992 · Mar 10, 2021
Continuation 16332145
Related Publication 20220191414A1 · Jun 16, 2022
Cited By (2)
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