Display device
A display device includes a first transistor including a gate electrode, a second transistor including a lower gate electrode, an upper gate electrode, and a first end portion electrically connected to an end portion of the first transistor, a lower gate signal line extending in a first direction, an upper gate signal line disposed on the lower gate signal line and extending in a first direction, and a first connection pattern disposed on the upper gate signal line, electrically connecting the gate electrode and a second end portion of the second transistor, and intersecting the lower gate signal line and the upper gate signal line. An entirety of the upper gate signal line overlaps a part of the lower gate signal line in an overlapping area in which the lower gate signal line or the upper gate signal line overlaps the first connection pattern.
1. A display device, comprising:
a first transistor including:
a first active layer disposed on a substrate; and
a gate electrode disposed on the first active layer;
an insulation layer disposed on the gate electrode;
a second transistor including:
a lower gate electrode disposed on the insulation layer;
a second active layer disposed on the lower gate electrode, a first end portion of the second active layer being electrically connected to an end portion of the first active layer; and
an upper gate electrode disposed on the second active layer;
a lower gate signal line extending in a first direction, a portion of the lower gate signal line forming the lower gate electrode;
an upper gate signal line disposed on the lower gate signal line and extending in the first direction, a portion of the upper gate signal line forming the upper gate electrode; and
a first connection pattern disposed on the upper gate signal line and connecting the gate electrode and a second end portion of the second active layer, wherein
a first area in which the lower gate signal line and the first connection pattern overlap each other is within a second area in which the upper gate signal line and the first connection pattern overlap each other, in a plan view, and
a width of the upper gate sianal line overlapping the first connection pattern is greater than a width of the lower gate signal line overlapping the first connection pattern.
2. The display device of claim 1 , wherein the first connection pattern intersects the lower gate signal line and the upper gate signal line in a second direction intersecting the first direction.
3. The display device of claim 2 , wherein a difference between the width of the upper gate signal line and the width of the lower gate signal line is greater than about 1 μm.
4. The display device of claim 2 , wherein the first connection pattern extends in the first area in the second direction.
5. The display device of claim 2 , wherein
the widths of the lower gate signal line both inside and outside of the first area in the second direction are substantially equal, and
the widths of the upper gate signal line both inside and outside of the second area in the second direction are substantially equal.
6. The display device of claim 2 , wherein the lower gate signal line is recessed in the second direction in the first area in the plan view.
7. The display device of claim 2 , wherein the upper gate signal line protrudes in the second direction in the second area in the plan view.
8. The display device of claim 1 , wherein
the first active layer of the first transistor includes polycrystalline silicon, and
the second active layer of the second transistor includes an oxide semiconductor.
9. The display device of claim 1 , further comprising:
a second connection pattern electrically connecting the end portion of the first active layer and the first end portion of the second active layer,
wherein the first connection pattern and the second connection pattern are disposed on a same layer.
10. A display device, comprising:
a first transistor including:
a first active layer disposed on a substrate; and
a gate electrode disposed on the first active layer;
an insulation layer disposed on the gate electrode;
a second transistor including:
a lower gate electrode disposed on the insulation layer;
a second active layer disposed on the lower gate electrode, a first end portion of the second active layer being electrically connected to an end portion of the first active layer; and
an upper gate electrode disposed on the second active layer;
a lower gate signal line extending in a first direction, a portion of the lower gate signal line forming the lower gate electrode;
an upper gate signal line disposed on the lower gate signal line and extending in the first direction, a portion of the upper gate signal line forming the upper gate electrode; and
a first connection pattern disposed on the upper gate signal line and connecting the gate electrode and a second end portion of the second active layer, wherein
a second area in which the upper gate signal line and the first connection pattern overlap each other is within a first area in which the lower gate signal line and the first connection pattern overlap each other, in a plan view, and
a width of the upper gate signal line overlapping the first connection pattern is less than a width of the lower gate signal ine overlapping the first connection pattern.
11. The display device of claim 10 , wherein the first connection pattern intersects the lower gate signal line and the upper gate signal line in a second direction intersecting the first direction.
12. The display device of claim 11 , wherein a difference between the width of the lower gate signal line and the width of the upper gate signal line is greater than about 1 μm.
13. The display device of claim 11 , wherein the first connection pattern extends in the first area in the second direction.
14. The display device of claim 11 , wherein
the widths of the lower gate signal line both inside and outside of the first area in the second direction are substantially equal, and
the widths of the upper gate signal line both inside and outside of the second area in the second direction are substantially equal.
15. The display device of claim 11 , wherein the lower gate signal line protrudes in the second direction in the first area in the plan view.
16. The display device of claim 11 , wherein the upper gate signal line is recessed in the second direction in the second area in the plan view.
17. The display device of claim 10 , wherein
the first active layer of the first transistor includes polycrystalline silicon, and
the second active layer of the second transistor includes an oxide semiconductor.
18. The display device of claim 10 , further comprising:
a second connection pattern electrically connecting the end portion of the first active layer and the first end portion of the second active layer,
wherein the first connection pattern and the second connection pattern are disposed on a same layer.