Bipolar transistor

1. A method of manufacturing a bipolar transistor, comprising:

forming a first cavity in a semiconductor substrate;

depositing a doped polysilicon layer on walls and a bottom of the first cavity and forming a first portion of a collector in the semiconductor substrate;

filling a remaining part of the first cavity with an insulating material to form an insulating trench over the doped polysilicon layer and the first portion of the collector; and

forming a second portion of the collector from semiconductor material which fills a second cavity that crosses through the insulating material of the insulating trench and the doped polysilicon layer, wherein a bottom of the second portion of the collector is in physical contact with the first portion of the collector.

2. The method of claim 1 , wherein forming the first portion of the collector comprises diffusing dopants of the doped polysilicon layer into the semiconductor substrate.

3. The method of claim 2 , wherein the doped polysilicon layer provides a substantially homogeneously doped region and wherein the first portion of the collector comprises a gradually doped region formed by the diffused dopants in the semiconductor substrate that is at least partially in contact with said substantially homogeneously doped region.

4. The method of claim 3 , wherein the bottom of the second portion of the collector is in physical contact with a top of the gradually doped region.

5. The method of claim 1 , wherein forming of the second portion of the collector comprises:

etching a portion of the doped polysilicon layer laterally away from the second cavity; and

epitaxially growing the semiconductor material of the second portion of the collector to form a first air pocket underneath the insulating material of the insulating trench.

6. The method of claim 5 , wherein the first air pocket is laterally delimited between the second portion of the collector and a remaining portion of the doped polysilicon layer and vertically delimited between the insulating material of the insulating trench and the bottom of the first cavity at the semiconductor substrate.

7. The method of claim 1 , wherein forming of the second portion of the collector comprises:

forming said second cavity by etching that extends to cross through the insulating trench; and

filling the second cavity with the semiconductor material for the second portion of the collector.

8. The method of claim 7 , wherein the forming of the first portion of the collector is performed before the etching of the second cavity.

9. The method of claim 1 , further comprising forming a conduction element over the insulating trench and wherein forming the second portion of the collector comprises:

etching a portion of the conduction element laterally away from the second cavity; and

epitaxially growing the semiconductor material of the second portion of the collector to form a second air pocket in a region where the portion of the conduction element is etched.

10. A bipolar transistor, comprising:

a semiconductor substrate including a first cavity;

a doped polysilicon layer on walls and a bottom of the first cavity;

a first portion of a collector in the semiconductor substrate below the first cavity;

an insulating material filling the first cavity to form an insulating trench over the doped polysilicon layer and the first portion of the collector; and

a semiconductor material in a second cavity which crosses through the insulating trench forming a second portion of the collector for the bipolar transistor, wherein a bottom of the second portion of the collector is in physical contact with a top of the first portion of the collector.

11. The bipolar transistor of claim 10 , a first air pocket underneath the insulating material of the insulating trench.

12. The bipolar transistor of claim 11 , wherein the first air pocket is laterally delimited between the second portion of the collector and a portion of the doped polysilicon layer and vertically delimited between the insulating material of the insulating trench and the first portion of the collector in the semiconductor substrate.

13. The bipolar transistor of claim 10 , wherein the doped polysilicon layer provides a substantially homogeneously doped region and wherein the first portion of the collector comprises a gradually doped region that is at least partially in contact with said substantially homogeneously doped region.

14. The bipolar transistor of claim 10 , further comprising a conduction element over the insulating trench, wherein the conduction element includes an opening forming a second air pocket between the second portion of the collector and the conduction element.

15. The bipolar transistor of claim 10 , wherein the doped polysilicon layer comprises a homogeneous doped region with a doping concentration in a range of 10 19 to 10 20 dopants/cm 3 .

16. The method of claim 2 , wherein the doped polysilicon layer comprises a homogeneous doped region with a doping concentration in a range of 10 19 to 10 20 dopants/cm 3 .