Page buffer circuits of three-dimensional memory device
The present disclosure provides buffer circuits of 3D NAND memory device. In some embodiments, the buffer circuit comprises a first bit line segment sensing branch connected to a first bit line segment and including a low-voltage latch, and a second bit line segment sensing branch connected to a second bit line segment and including a sensing latch. The first bit line segment sensing branch and the second bit line segment sensing branch are parallel connected to a sensing node of the page buffer circuit.
1. A page buffer circuit of a memory device, comprising:
a first bit line segment sensing branch connected to a first bit line segment and including a low-voltage latch; and
a second bit line segment sensing branch connected to a second bit line segment and including a sensing latch;
wherein the first bit line segment sensing branch and the second bit line segment sensing branch are parallel connected to a sensing node of the page buffer circuit.
2. The page buffer circuit of claim 1 , wherein each of the first and second bit line segment sensing branches comprises a bit line pre-charge path.
3. The page buffer circuit of claim 1 , wherein the first bit line segment is aligned with the second bit line segment along a bit line direction.
4. The page buffer circuit of claim 1 , wherein the first bit line segment and the second bit line segment are separated connected with a same memory cell string.
5. The page buffer circuit of claim 4 , wherein the memory device is a three-dimensional NAND memory device and the memory cell string is a vertical memory cell stack string.
6. The page buffer circuit of claim 1 , wherein the first and second bit line segment sensing branches are commonly connected to a cache latch.
7. The page buffer circuit of claim 1 , further comprising:
a third bit line segment sensing branch connected to a third bit line segment and including a sense latch;
wherein the first, the second, and the third bit line segment sensing branches are parallel connected to the sensing node of the page buffer circuit.
8. The page buffer circuit of claim 7 , wherein the first, the second, and the third bit line segments are aligned with each other along a bit line direction.
9. The page buffer circuit of claim 7 , wherein the first, the second, and the third bit line segments are separated connected with a same memory cell string.
10. The page buffer circuit of claim 7 , wherein the first, the second, and the third bit line segment sensing branches are commonly connected to a cache latch.
11. A memory device, comprising:
a plurality of bit lines parallel extending along a bit line direction, each bit line of the plurality of bit lines comprising a first bit line segment and a second bit line segment; and
a plurality of page buffers each corresponding to one of the plurality of bit lines;
wherein the first and second bit line segments are commonly connected to a same corresponding page buffer.
12. The memory device of claim 11 , wherein each page buffer comprises:
a first bit line segment sensing branch connected to the first bit line segment and including a low-voltage latch; and
a second bit line segment sensing branch connected to the second bit line segment and including a sense latch;
wherein the first bit line segment sensing branch and the second bit line segment sensing branch are parallel connected to a sensing node of the page buffer circuit.
13. The memory device of claim 12 , wherein each of the first and second bit line segment sensing branches comprises a bit line pre-charge path.
14. The memory device of claim 12 , wherein the first and second bit line segment sensing branches are commonly connected to a cache latch.
15. The memory device of claim 12 , wherein each page buffer further comprises:
a third bit line segment sensing branch connected to a third bit line segment and including a sense latch;
wherein the first, the second, and the third bit line segment sensing branches are parallel connected to the sensing node of the page buffer circuit.
16. The memory device of claim 15 , wherein the first, the second, and the third bit line segments are separated connected with a same memory cell string.
17. The memory device of claim 15 , wherein the first, the second, and the third bit line segment sensing branches are commonly connected to a cache latch.
18. The memory device of claim 11 , further comprising:
a plurality of memory cell strings;
wherein the first bit line segment and the second bit line segment are separated connected with a same memory cell string.
19. The memory device of claim 18 , wherein the memory device is a three-dimensional NAND memory device and the plurality of memory cell strings are vertical memory cell stack strings.
20. A memory system, comprising:
a memory device, comprising:
a plurality of bit lines parallel extending along a bit line direction, each bit line of the plurality of bit lines comprising a first bit line segment and a second bit line segment, and
a plurality of page buffers each corresponding to one of the plurality of bit lines;
wherein the first and second bit line segments are commonly connected to a same corresponding page buffer; and
a memory controller configured to simultaneously perform pre-charge operations, develop operations, and sensing operations, by at least two bit line segment sensing branches in a one page buffer circuit, on the first and second bit line segments of one corresponding bit line.