Display device and manufacturing method thereof
A display device includes: a substrate; a transistor disposed on the substrate; a first electrode connected to the transistor; an emission layer disposed on the first electrode; a second electrode disposed on the emission layer; a common voltage line connected to the second electrode; and a third electrode and a fourth electrode disposed between the common voltage line and the second electrode.
1. A display device comprising:
a substrate;
a transistor disposed on the substrate;
a first electrode connected to the transistor;
an emission layer disposed on the first electrode;
a second electrode disposed on the emission layer;
a common voltage line connected to the second electrode; and
a third electrode and a fourth electrode disposed between, and electrically connected to the common voltage line and the second electrode, wherein
the common voltage line includes a bottom surface facing the substrate, a top surface opposite the bottom surface and facing away from the substrate, and a side surface connecting the top surface and the bottom surface;
the third electrode comprises a first auxiliary electrode in direct contact with the side surface of the common voltage line.
2. The display device of claim 1 , wherein
a distil end of the third electrode is in direct contact with the side surface of the common voltage line, and
the fourth electrode comprises a second auxiliary electrode disposed on the first auxiliary electrode.
3. The display device of claim 2 , wherein:
the first auxiliary electrode includes a first inclined surface adjacent to the side surface of the common voltage line; and
the second auxiliary electrode includes a second inclined surface adjacent to the first inclined surface of the first auxiliary electrode, and wherein:
the first inclined surface of the first auxiliary electrode is disposed at a first inclination angle, the side surface of the common voltage line is disposed at a second inclination angle, the first inclination angle being smaller than the second inclination angle, and
the second inclined surface of the second auxiliary electrode is disposed at a third inclination angle smaller than the second inclination angle.
4. The display device of claim 3 , wherein
the second electrode is in contact with the second auxiliary electrode.
5. The display device of claim 1 , wherein the common voltage line comprises:
a lower layer,
an intermediate layer disposed on the lower layer, and
an upper layer disposed on the intermediate layer, and
the upper layer has a width wider than that of the intermediate layer.
6. The display device of claim 5 , wherein:
the third electrode is in contact with a side surface of the intermediate layer, and
the fourth electrode is disposed on the third electrode.
7. The display device of claim 6 , wherein, the lower layer has a width wider than that of the intermediate layer.
8. The display device of claim 1 , further comprising:
a first layer disposed on the first electrode, the first layer including a pixel opening overlapping the first electrode, and
a second layer disposed on the first layer,
wherein a second auxiliary electrode and the second layer are disposed on a same layer.
9. The display device of claim 8 , wherein:
the first layer comprises a bank layer having an upper surface,
the second layer comprises a separator layer having an edge adjacent to the pixel opening of the bank layer, and
the edge of the separator layer has a lower surface adjacent to the pixel opening and not in contact with the upper surface of the bank layer.
10. The display device of claim 9 , wherein the lower surface of the edge of the separator layer adjacent to the pixel opening is in contact with the second electrode.
11. The display device of claim 10 , wherein a portion of the bank layer adjacent to the pixel opening has a thickness thinner than that of the remaining portion of the bank layer.
12. The display device of claim 8 , wherein the second auxiliary electrode is connected to the second layer.
13. The display device of claim 8 , wherein a portion of the emission layer overlapping the second layer and a portion of the emission layer not overlapping the second layer are separated from each other.
14. The display device of claim 8 , wherein a portion of the emission layer overlapping the common voltage line and a portion of the emission layer not overlapping the common voltage line are separated from each other.
15. The display device of claim 8 , wherein a portion of the second electrode overlapping the second layer and a portion of the second electrode not overlapping the second layer are connected to each other.
16. The display device of claim 8 , wherein a portion of the second electrode overlapping the common voltage line and a portion of the second electrode not overlapping the common voltage line are separated from each other.
17. The display device of claim 8 , wherein the emission layer comprises:
a plurality of light emitting units, and
a charge generating layer disposed between the plurality of light emitting units.
18. The display device of claim 1 , wherein the transistor comprises:
a semiconductor disposed on the substrate,
a gate electrode overlapping the semiconductor, and
a source electrode and a drain electrode connected to the semiconductor, and
wherein the common voltage line, the source electrode, and the drain electrode are disposed on a same layer.
19. The display device of claim 1 , wherein the third electrode and the first electrode are formed of a same material.
20. A method of manufacturing a display device, the method comprising the steps of:
forming a transistor on a substrate;
forming a common voltage line spaced apart from the transistor on the substrate;
forming a first electrode connected to the transistor;
forming a third electrode electrically connected to the common voltage line;
forming a fourth electrode on and electrically connected to the third electrode;
forming an emission layer on the first electrode; and
forming a second electrode on the emission layer and the fourth electrode, wherein
the common voltage line includes a bottom surface facing the substrate, a top surface opposite the bottom surface and facing away from the substrate, and a side surface connecting the top surface and the bottom surface:
the third electrode comprises a first auxiliary electrode in direct contact with the side surface of the common voltage line.
21. The method of claim 20 , wherein a distil end of the third electrode is in direct contact with the side surface of the common voltage line.
22. The method of claim 20 , wherein:
the third electrode comprises a first auxiliary electrode having a first inclined surface adjacent to a side surface of the common voltage line; and
the fourth electrode comprises a second auxiliary electrode having a second inclined surface adjacent to the first inclined surface of the first auxiliary electrode, and wherein:
the first inclined surface of the first auxiliary electrode is disposed at a first inclination angle,
the side surface of the common voltage line is disposed at a second inclination angle, the first inclination angle being smaller than the second inclination angle, and
the second inclined surface of the second auxiliary electrode is disposed at a third inclination angle smaller than the first inclination angle.
23. The method of claim 22 , wherein the second electrode is in contact with the second auxiliary electrode.
24. The method of claim 20 , wherein the common voltage line comprises:
a lower layer,
an intermediate layer disposed on the lower layer, and
an upper layer disposed on the intermediate layer, and
the intermediate layer is made of a different material from that of the upper layer, and
the intermediate layer has a width that becomes narrower than that of the upper layer by etching the intermediate layer after forming the common voltage line.
25. The method of claim 24 , wherein the third electrode is in contact with a side surface of the intermediate layer.
26. The method of claim 25 , wherein:
the intermediate layer is made of a different material from that of the lower layer, and
the intermediate layer has a width that becomes narrower than that of the lower layer by an etching process of the intermediate layer.
27. The method of claim 20 , further comprising the steps of:
forming a first layer on the first electrode;
forming a pixel opening overlapping the first electrode in the first layer;
forming a second layer on the first layer; and
performing an ashing process on the first layer to remove a portion of the first layer disposed below the second layer,
wherein the fourth electrode and the second layer are made of a same material and are formed by a same process.
28. The method of claim 27 , wherein the emission layer comprises:
a plurality of light emitting units, and
a charge generating layer disposed between the plurality of light emitting units.
29. The method of claim 20 , wherein the transistor comprises:
a semiconductor disposed on the substrate,
a gate electrode overlapping the semiconductor, and
a source electrode and a drain electrode connected to the semiconductor, and
the common voltage line and the source electrode and the drain electrode are made of a same material and are formed by a same process.
30. The method of claim 20 , wherein the third electrode and the first electrode are made of a same material and are formed by a same process.