IP Library › Granted Patent US 12,232,433
Granted Patent B2
US 12,232,433 · App. 17/689,604 · Granted Feb 18, 2025

Semiconductor device and method of forming a semiconductor device

Inventors: Artur Wroblewski (Munich, DE); Joel Hatsch (Holzkirchen, DE); Christoph Saas (Munich, DE); Stefan Seidl (Munich, DE)
Assignee: Infineon Technologies AG
H10N70/826H01L28/24H10B63/00H10N70/021H10N70/8833
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Quick Facts
Patent No.
US 12,232,433
App. No.
17/689,604
Granted
Feb 18, 2025
Kind
B2
Abstract

A semiconductor device including a carrier having two main surfaces situated opposite one another, a circuit, having at least one resistance element, in and/or on the carrier, wherein the at least one resistance element has a longitudinal axis extending vertically between the main surfaces of the carrier, and a current limiting circuit configured to limit a current flowing through the resistance element to a value at which it is ensured that an electrical resistance of the resistance element remains substantially unchanged.

Claims (46)

1. A semiconductor device, comprising:

a carrier having two main surfaces situated opposite one another;

a circuit, comprising at least one resistance element, in and/or on the carrier, wherein the at least one resistance element has a longitudinal axis extending vertically between the main surfaces of the carrier; and

a current limiting circuit configured to limit a current flowing through the resistance element to a value at which it is ensured that an electrical resistance of the resistance element remains substantially unchanged.

2. The semiconductor device as claimed in claim 1 , wherein the at least one resistance element is formed as an RRAM element.

3. The semiconductor device as claimed in claim 2 , wherein the RRAM element is in an unformed state, in a formed high-resistance state or in a formed low-resistance state.

4. The semiconductor device as claimed in claim 1 , wherein the at least one resistance element comprises two or more resistance elements connected or connectable in parallel.

5. The semiconductor device as claimed in claim 1 , wherein the at least one resistance element comprises two or more resistance elements connected or connectable in series.

6. The semiconductor device as claimed in claim 1 , wherein the resistance of the resistance element is in a range of between 1 kΩ and 100 MΩ.

7. The semiconductor device as claimed in claim 1 , wherein the analog circuit comprises at least one additional circuit element.

8. The semiconductor device as claimed in claim 7 , wherein the at least one additional circuit element comprises at least one circuit element selected from a group of circuit elements consisting of:

a capacitor;

a diode;

a transistor; and

an operational amplifier.

9. The semiconductor device as claimed in claim 1 , wherein the circuit is formed as an analog circuit element selected from a group of analog circuits consisting of:

a filter;

a voltage divider;

a bias voltage generator;

a voltage-current converter;

a current-voltage converter;

a reference voltage source;

a reference current source;

a load;

an inverter;

a current limiter;

a noninverting amplifier;

a summing amplifier;

a subtracting amplifier;

an integrator; and

a differentiator.

10. The semiconductor device as claimed in claim 1 , wherein the at least one resistance element is formed in a frontend insulating layer.

11. The semiconductor device as claimed in claim 1 , wherein the at least one resistance element is formed in a backend insulating layer.

12. The semiconductor device as claimed in claim 1 , wherein the circuit is an analog circuit.

13. The semiconductor device as claimed in claim 1 , wherein a main current flow passes along the vertical longitudinal axis.

14. A method for forming a semiconductor device, the method comprising:

providing a carrier having two main surfaces situated opposite one another;

forming a circuit, comprising at least one resistance element, in and/or on the carrier, wherein the at least one resistance element has a longitudinal axis extending vertically between the main surfaces of the carrier; and

providing a current limiting circuit configured to limit a current flowing through the resistance element to a value at which it is ensured that an electrical resistance of the resistance element remains substantially unchanged.

15. The method as claimed in claim 14 , wherein the resistance element is formed as part of frontend processing.

16. The method as claimed in claim 14 , wherein the resistance element is formed as part of backend processing.

17. The method as claimed in claim 14 , wherein the at least one resistance element is formed as an RRAM element.

18. The method as claimed in claim 17 , wherein the RRAM element is in an unformed state.

19. The method as claimed in claim 17 , furthermore comprising:

forming the RRAM element into a high-resistance state or into a low-resistance state;

wherein the current limiting circuit is provided after forming the RRAM element.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 7, 2022
From: WROBLEWSKI, ARTUR; HATSCH, JOEL; SAAS, CHRISTOPH; SEIDL, STEFAN
To: INFINEON TECHNOLOGIES AG
Reel/Frame 059534/0501 →
Priority Claims (1)
DE 102021105680.2 · Mar 9, 2021 · national
Continuity (1)
Related Publication 20220293852A1 · Sep 15, 2022
References Cited (3)
US 20170207207A1 · Hsiao et al. · 2017 [cited by applicant]
US 20170330915A1 · Chen · 2017 [cited by applicant]
German Patent Office, Office Action issued for DE 102021105680.2, 8 pgs., dated Oct. 15, 2021. [cited by applicant]