IP Library › Granted Patent US 11,899,965
Granted Patent B2
US 11,899,965 · App. 17/691,642 · Granted Feb 13, 2024

Enhanced k-SAT solver using analog content addressable memory

Inventors: Giacomo Pedretti (Verbania, IT); John Paul Strachan (San Carlos, CA); Thomas Maurits M. Van Vaerenbergh (Saint-Josse-ten-Noode, BE); Catherine E. Graves (Milpitas, CA)
Assignee: Hewlett Packard Enterprise Development LP
G06F3/0655G06F3/0604G06F3/0673G06N3/063
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Quick Facts
Patent No.
US 11,899,965
App. No.
17/691,642
Granted
Feb 13, 2024
Kind
B2
Abstract

A system for facilitating an enhanced k-SAT solver is provided. The system can include a set of analog content addressable memory (aCAM) modules that can represent an expression in a conjunctive normal form (CNF), wherein a respective aCAM module corresponds to a clause of the expression. The system can also include a set of data lines that can provide input candidate values to the set of aCAM modules. A controller of the system can program the set of aCAM modules with respective analog values to represent the expression. The system can also include sensing logic block to determine a distance of a current solution from a target solution based on a combination of respective outputs from the set of aCAM modules. The controller can then iteratively modify an input value for a subset of data lines until the current solution converges based on a convergence condition.

Claims (41)

1. A system, comprising:

a set of analog content addressable memory (aCAM) modules to represent an expression in a conjunctive normal form (CNF), wherein a respective aCAM module corresponds to a clause of the expression;

a set of data lines to provide input candidate values to the set of aCAM modules;

a controller to program the set of aCAM modules with respective analog values to represent the expression;

a sensing logic block to determine a distance of a current solution from a target solution based on a combination of respective outputs from the set of aCAM modules; and

wherein the controller is further to iteratively modify an input value for a subset of data lines until the current solution converges based on a convergence condition.

2. The system of claim 1 , wherein the distance includes a voltage distance, and wherein the convergence condition includes a voltage value of zero calculated based on the respective outputs.

3. The system of claim 1 , wherein a respective aCAM module includes a plurality of aCAM cells, and wherein a respective aCAM cell is associated with a variable of a clause of the expression indicated by the aCAM module.

4. The system of claim 3 , wherein the aCAM cell includes one or more tunable resistance devices (TRDs), wherein a respective TRD facilitates non-volatile storage of continuous analog value.

5. The system of claim 4 , wherein the TRD includes one of:

a memristor;

a memristor;

a memtransistor; and

a memory component in a neuromorphic memory device.

6. The system of claim 1 , wherein the controller is further to determine whether modifying the input value decreases the distance from the target solution based on the combination of the respective outputs.

7. The system of claim 6 , wherein the controller is further to increase or decrease the input value in response to sensing an increased distance from the target solution.

8. The system of claim 1 , further comprising a gradient logic block to, in response to the combination of the respective outputs not changing for a number of iterations, incorporate noise to the input candidate values, thereby facilitating gradient descent.

9. The system of claim 1 , wherein the set of aCAM modules are organized in a hierarchical array, wherein a respective element of the hierarchical array comprises a subset of the aCAM modules.

10. The system of claim 9 , wherein the sensing logic block is further to determine the combination of the respective outputs by adding respective outputs of the respective element of the hierarchical array.

11. An apparatus, comprising:

a control system; and

an accelerator, comprising:

a set of analog content addressable memory (aCAM) modules to represent an expression in a conjunctive normal form (CNF), wherein a respective aCAM module corresponds to a clause of the expression;

a set of data lines to provide input candidate values to the set of aCAM modules; and

sensing circuitry to determine a distance of a current solution from a target solution based on a combination of respective outputs from the set of aCAM modules; and

wherein the control system is to:

program the set of aCAM modules with respective analog values to represent the expression; and

iteratively modify an input value for a subset of data lines until the current solution converges based on a convergence condition.

12. The apparatus of claim 11 , wherein the distance includes a voltage distance, and wherein the convergence condition includes a voltage value of zero calculated based on the respective outputs.

13. The apparatus of claim 11 , wherein a respective aCAM module includes a plurality of aCAM cells, and wherein a respective aCAM cell is associated with a variable of a clause of the expression indicated by the aCAM module.

14. The apparatus of claim 13 , wherein the aCAM cell includes one or more tunable resistance devices (TRDs), wherein a respective TRD facilitates non-volatile storage of continuous analog value.

15. The apparatus of claim 14 , wherein the TRD includes one of:

a memristor;

a memristor;

a memtransistor; and

a memory component in a neuromorphic memory device.

16. The apparatus of claim 11 , wherein the controller is further to determine whether modifying the input value decreases the distance from the target solution based on the combination of the respective outputs.

17. The apparatus of claim 16 , wherein the control system is further to increase or decrease the input value in response to sensing an increased distance from the target solution.

18. The apparatus of claim 11 , wherein the accelerator further comprises gradient circuitry to, in response to the combination of the respective outputs not changing for a number of iterations, incorporate noise to the input candidate values, thereby facilitating gradient descent.

19. The apparatus of claim 11 , wherein the set of aCAM modules are organized in a hierarchical array, wherein a respective element of the hierarchical array comprises a subset of the aCAM modules.

20. The apparatus of claim 19 , wherein the sensing circuitry is further to determine the combination of the respective outputs by adding respective outputs of the respective element of the hierarchical array.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 23, 2022
From: PEDRETTI, GIACOMO; STRACHAN, JOHN PAUL; VAN VAERENBERGH, THOMAS MAURITS M.; GRAVES, CATHERINE E.
To: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Reel/Frame 059380/0547 →
Continuity (1)
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