IP Library › Granted Patent US 12,000,455
Granted Patent B2
US 12,000,455 · App. 17/691,805 · Granted Jun 4, 2024

Systems and methods for reducing vibration of apparatuses

Inventors: Yi Chen Ho (Taichung, TW); Chih Ping Liao (Hsinchu, TW); Chien Ting Lin (Hsinchu, TW); Jie-Ying Yang (Yunlin County, TW); Wei-Ming Wang (Hsinchu, TW); Ker-Hsun Liao (Hsinchu, TW); Chi-Hsun Lin (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
F16F7/10F16F2222/08
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Quick Facts
Patent No.
US 12,000,455
App. No.
17/691,805
Granted
Jun 4, 2024
Kind
B2
Abstract

A method that includes measuring vibration levels in a semiconductor manufacturing apparatus, determining one or more sections of the semiconductor manufacturing apparatus that vibrate at levels greater than a predetermined vibration level, and reducing the vibration levels in the one or more sections to be at or within the predetermined vibration level by coupling one or more weights to an external surface of the semiconductor manufacturing apparatus in the one or more sections.

Claims (34)

1. A method, comprising:

measuring vibration levels in semiconductor manufacturing apparatus;

determining one or more sections of the semiconductor manufacturing apparatus that vibrate at levels greater than a predetermined vibration level; and

reducing the vibration levels in the one or more sections to be at or within the predetermined vibration level by coupling a plurality of weights to an external surface of the semiconductor manufacturing apparatus in the one or more sections, the plurality of weights being coupled to opposite lateral walls of the semiconductor manufacturing apparatus.

2. The method of claim 1 , wherein the plurality of weights are coupled spaced from a ground surface on which the semiconductor manufacturing apparatus is positioned.

3. The method of claim 1 , wherein each weight of the plurality of weights is coupled opposite another weight of the plurality of weights.

4. The method of claim 3 , wherein the opposite lateral walls include external surfaces of the semiconductor manufacturing apparatus and the weights coupled to the opposite lateral walls face toward each other.

5. The method of claim 3 , wherein the weights attached to the opposite lateral walls face away from each other.

6. The method of claim 1 , further comprising increasing an overall weight amount attached to the semiconductor manufacturing apparatus by coupling additional weights to existing weights coupled to the semiconductor manufacturing apparatus.

7. The method of claim 1 , wherein each weight of the plurality of weights has a same weight value.

8. The method of claim 1 , wherein the semiconductor manufacturing apparatus is placed on an anti-vibration platform that is placed on a ground surface, and method includes coupling the plurality of weights between a base of the semiconductor manufacturing apparatus and an upper surface of the anti-vibration platform.

9. The method of claim 8 , wherein the plurality of weights are spaced from the upper surface of the anti-vibration platform and the ground surface.

10. A method, comprising:

attaching a first weight to a first external surface of a semiconductor manufacturing apparatus;

attaching a second weight to a second external surface of the semiconductor manufacturing apparatus, the second external surface being opposite to the first external surface and the first external surface and the second external surface forming opposite lateral walls of the semiconductor manufacturing apparatus;

measuring vibration levels in portions of the semiconductor manufacturing apparatus having the first weight and the second weight; and

increasing the first weight and the second weight when the vibration levels are greater than a predetermined level.

11. The method of claim 10 , wherein the first weight is attached exactly opposite the second weight.

12. The method of claim 10 , further comprising:

attaching a third weight on the first external surface and a fourth weight on the second external surface to reduce the vibration levels to be less than or equal to the predetermined level.

13. The method of claim 10 , wherein a plurality of weights are attached to the first external surface and the second external surface, the plurality of weights including the first weight and the second weight, and

a same number of weights are attached to the first external surface and the second external surface.

14. The method of claim 13 , wherein each weight on the first external surface has a corresponding weight on the second external surface and attached exactly opposite to each other.

15. The method of claim 10 , wherein the first weight and the second weight are attached separated from a ground surface on which the semiconductor manufacturing apparatus is positioned.

16. The method of claim 10 , wherein increasing the first weight and the second weight comprises:

coupling additional weights to each of the first weight and the second weight.

17. The method of claim 10 , wherein the first weight and the second weight have a same weight value.

18. Semiconductor manufacturing apparatus, comprising:

a first lateral wall;

a second lateral wall opposite the first lateral wall, the first lateral wall and the second lateral wall forming external surfaces of the semiconductor manufacturing apparatus; and

one or more weights each attached to the external surfaces formed by the first lateral wall and the second lateral wall, wherein the weights are attached on locations on the semiconductor manufacturing apparatus that maximize a reduction in vibrations of the semiconductor manufacturing apparatus at those locations.

19. The semiconductor manufacturing apparatus of claim 18 , wherein each weight is attached separated from a ground surface on which the semiconductor manufacturing apparatus is positioned.

20. The semiconductor manufacturing apparatus of claim 18 , further comprising:

one or more additional weights coupled to the one or more weights to increase an overall weight on the semiconductor manufacturing apparatus.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 4, 2024
From: HO, YI CHEN; LIAO, CHIH PING; LIN, CHIEN TING; YANG, JIE-YING; WANG, WEI-MING; LIAO, KER-HSUN; LIN, CHI-HSUN
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 067009/0277 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 10, 2022
From: HO, YI CHEN; LIAO, CHIH PING; LIN, CHIEN TING; YANG, JIE-YING; WANG, WEI-MING; LIAO, KER-HSUN; LIN, CHI-HSUN
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 059227/0670 →
Continuity (1)
Related Publication 20230287952A1 · Sep 14, 2023
Cited By (1)
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