IP Library Granted Patent US 11,671,599
Granted Patent B2
US 11,671,599 · App. 17/695,114 · Granted Jun 6, 2023

Data encoding and decoding

Inventors: James Alexander Gamei (Surrey, GB); Karl James Sharman (Newbury, GB)
Assignee: Sony Group Corporation
H04N19/13H03M7/4018H04N19/107H04N19/117H04N19/129H04N19/159H04N19/52H04N19/593H04N19/61H04N19/625H04N19/91
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Quick Facts
Patent No.
US 11,671,599
App. No.
17/695,114
Granted
Jun 6, 2023
Kind
B2
Abstract

A method of data encoding input data values of a data set for encoding includes selecting one of a plurality of complementary sub-ranges of a set of code values according to the value of a current input data value, the set of code values being defined by a range variable, assigning the current input data value to a code value within the selected sub-range, modifying the set of code values in dependence upon the assigned code value and the size of the selected sub-range, detecting whether the range variable defining the set of code values is less than a predetermined minimum size and if so, successively increasing the range variable so as to increase the size of the set of code values until it has at least the predetermined minimum size and outputting an encoded data bit in response to each such size-increasing operation, and after encoding a group of input data values, setting the range variable to a value selected from a predetermined subset of available range variable values, each value in the subset having at least one least significant bit equal to zero.

Claims (30)

1. A method of decoding a sequence of data values comprising Context-Based Adaptive Binary Arithmetic Coding (CABAC) encoded data values and CABAC bypass data values, comprising:

prior to decoding CABAC bypass data values in the sequence of data values, setting a range variable value of a CABAC decoder to a predetermined value, which has at least one significant bit equal to zero, and

treating a portion of the sequence of data values as a shift register and outputting CABAC bypass data values as sequential bit values to a decoded data stream.

2. The method according to claim 1 , wherein the predetermined value is a largest valid power of two value, which creates a sub-range for n-bit CABAC entropy decoding.

3. The method according to claim 1 , wherein the predetermined value is 256.

4. The method according to claim 1 , further comprising simultaneously decoding CABAC encoded data values and outputting CABAC bypass data values to form the decoded data stream.

5. The method according to claim 1 , wherein a state of the CABAC decoder is aligned to a bit boundary of the CABAC bypass data values of the sequence of data values.

6. The method according to claim 5 , wherein the state of the CABAC decoder includes a range variable value and an m_value.

7. The method according claim 5 , further comprising selectively treating the sequence of data values as bit-aligned.

8. The method according to claim 1 , wherein the sequence of data values comprises

transform coefficients.

9. The method according to claim 1 , wherein the sequence of data values comprises HEVC video data.

10. A non-transitory computer readable medium including computer program instructions, which when executed by a computer causes the computer to implement the method of claim 1 .

11. A data decoding apparatus configured to decode a sequence of data values comprising Context-Based Adaptive Binary Arithmetic Coding (CABAC) encoded data values and CABAC bypass data values, comprising:

a processor configured to:

prior to decoding CABAC bypass data values in the sequence of data values, set a range variable value of a CABAC decoder to 256, and

treat a portion of the sequence data values as a shift register and output CABAC bypass data values as sequential bit values to a decoded data stream.

12. The data decoding apparatus as claimed in claim 11 , further comprising: a memory wherein the decoded data stream is stored in the memory.

13. The data decoding apparatus as claimed in claim 11 , wherein the processor is further configured to simultaneously decode CABAC encoded data values and output CABAC bypass data values to form the decoded data stream.

14. The data decoding apparatus as claimed in claim 11 , wherein state values of the CABAC decoder are aligned to a bit boundary of the sequence of data values.

15. The data decoding apparatus as claimed in claim 14 , wherein the state values include a range variable value and m_value.

16. The data decoding apparatus as claimed in claim 14 , wherein the processor is further configured to selectively treat the sequence of data values as bit-aligned.

17. The data decoding apparatus as claimed in claim 14 , wherein the processor is further configured to selectively decode CABAC encoded data values and CABAC bypass data values in a non-bit aligned mode.

18. The data decoding apparatus as claimed in claim 11 , wherein the sequence of data values comprises HEVC video data or transform coefficients.

19. A video receiver for receiving a signal, the receiver comprising:

the data decoding apparatus of claim 11 .

20. A video capture apparatus comprising:

an image sensor;

a video encoder; and

the data decoding apparatus according to claim 11 .

Assignments (2)
CHANGE OF NAME Recorded Apr 5, 2022
From: SONY CORPORATION
To: SONY GROUP CORPORATION
Reel/Frame 059607/0044 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 30, 2022
From: GAMEI, JAMES ALEXANDER; SHARMAN, KARL JAMES
To: SONY CORPORATION
Reel/Frame 059444/0088 →
Priority Claims (1)
GB 1306334 · Apr 8, 2013 · national
Continuity (2)
Continuation 14778394
Related Publication 20220217351A1 · Jul 7, 2022