System and method for adaptive gate drive current circuit
In a switching regulator driver, a sense circuit has a transistor current input and a sense circuit output. A logic circuit has a logic circuit input and first and second outputs. The logic circuit input is coupled to the sense circuit output. A counter has a counter clock input, a counter control input and a counter output. The counter clock input is coupled to the first output. The counter control input is coupled to the second output. The counter is configured to provide a count value at the counter output. A programmable drive strength circuit has a drive strength circuit input and a transistor control output. The drive strength circuit input is coupled to the counter output. The programmable drive strength circuit is configured to adjust a drive current at the transistor control output based on the count value.
1. A device comprising:
a sense circuit having a sense circuit output;
a logic circuit having a logic circuit input, a first logic circuit output, and a second logic circuit output, the logic circuit input coupled to the sense circuit output, the logic circuit comprising an exclusive-NOR gate having a gate output coupled to the first logic circuit output;
a counter having a first counter input, a second counter input, and a counter output, the first counter input coupled to the first logic circuit output, the second counter input coupled to the second logic circuit output, and the counter configured to provide a count value at the counter output; and
a drive circuit having a drive circuit input coupled to the counter output, the drive circuit configured to produce a drive current based on the count value.
2. The device of claim 1 , further comprising a decoder coupled between the counter output and the drive circuit input.
3. The device of claim 1 , wherein the logic circuit is configured to: detect whether a rate of change of a drain current of a transistor is above a threshold; and responsive to the rate of change of the drain current being above the threshold, adjust the first logic circuit output or the second logic circuit output to change the count value.
4. The device of claim 1 , wherein the logic circuit is configured to:
detect whether a signal indicative of a rate of change of a drain current of a transistor is above first and second thresholds;
responsive to the signal being above the first and second thresholds, adjust the first logic circuit output or the second logic circuit output to increment the count value; and
responsive to the signal being below the first and second thresholds, adjust the first logic circuit output or the second logic circuit output to decrement the count value.
5. The device of claim 4 , wherein the logic circuit is configured to: responsive to the signal being between the first and second thresholds, adjust the first logic circuit output or the second logic circuit output to prevent the counter from incrementing or decrementing the count value.
6. The device of claim 1 , wherein the sense circuit includes a high-pass filter.
7. The device of claim 1 , wherein the logic circuit further comprises:
a first comparator having a comparator output and first and second comparator inputs, in which the comparator output is the second logic circuit output;
a second comparator having a second comparator output and third and fourth comparator inputs; and
a flip-flop having a flip-flop input and a flip-flop output, in which the flip-flop output is the first logic circuit output, and the flip-flop input is coupled to the gate output of the exclusive-NOR gate.
8. The device of claim 1 , wherein:
the logic circuit is configured to: detect whether a rate of change of a drain current of a transistor is above a threshold; and responsive to the rate of change of the drain current being above the threshold, adjust the first logic circuit output or the second logic circuit output to change the count value;
the drive circuit is configured to decrease the drive current responsive to the adjusted count value;
the device further comprises a switch node transition detection circuit configured to: detect whether the transistor has turned on; and responsive to detecting that the transistor has turned on, provide a signal to the logic circuit; and
the drive circuit is configured to increase the drive current at a control terminal of the transistor responsive to the provided signal.
9. The device of claim 1 , further comprising:
a comparator having a comparator output;
a delay circuit having a delay circuit output; and
a flip-flop having a first flip-flop input, a second flip-flop input, and a flip-flop output, the first flip-flop input coupled to the delay circuit output, and the second flip-flop input coupled to the comparator output.
10. The device of claim 9 , wherein the counter is a first counter, and the device further comprises a second counter having a third flip-flop input coupled to the flip-flop output.
11. A device comprising:
a sense circuit having a sense circuit output;
a first comparator having a first comparator output and a first comparator input, the first comparator input coupled to the sense circuit output;
a second comparator having a second comparator output and a second comparator input, the second comparator input coupled to the sense circuit output;
a logic gate having a logic gate output and first and second logic gate inputs, the first logic gate input coupled to the first comparator output, and the second logic gate input coupled to the second comparator output;
a first counter having a first counter input, a second counter input, and a first counter output, the first counter input coupled to the logic gate output, the second counter input coupled to the second comparator output;
a flip-flop having a flip-flop output;
a second counter having a third counter input and a second counter output, the third counter input coupled to the flip-flop output; and
a drive circuit having a drive circuit input, the drive circuit input coupled to the first counter output and the second counter output.
12. The device of claim 11 , wherein the logic gate is an exclusive-NOR gate.
13. The device of claim 11 , wherein the flip-flop is a first flip-flop, the device further comprising a second flip-flop having a flip-flop input, wherein the flip-flop input is coupled to the logic gate output.
14. The device of claim 11 , wherein the sense circuit includes a high-pass filter.
15. The device of claim 11 , further comprising:
a delay circuit having a delay circuit input and a delay circuit output, the delay circuit input coupled to the first counter output and the delay circuit output coupled to the drive circuit input.
16. A device comprising:
a sense circuit having a sense circuit output;
a logic circuit having a logic circuit input and first and second logic circuit outputs, the logic circuit input coupled to the sense circuit output;
a drive circuit having a drive circuit input and a drive circuit output; and
a counter having a first counter input, a second counter input, and a counter output, the first counter input coupled to the first logic circuit output, the second counter input coupled to the second logic circuit output, the counter output coupled to the drive circuit input, and the counter configured to provide a count value at the counter output; and wherein:
during a first phase, the drive circuit is configured to provide a fixed level of a drive current responsive to receiving a pulse for a time duration; and
responsive to the pulse ending, transitioning the device to a second phase, in which the drive circuit is configured to provide a variable level of the drive current at the drive circuit output responsive to the count value.
17. The device of claim 16 , further comprising a decoder coupled between the counter output and the drive circuit input, in which the decoder is configured to convert the count value to a signal, and the drive circuit is configured to receive the signal at the drive circuit input.
18. The device of claim 16 , wherein the logic circuit is configured to: detect whether a rate of change of a drain current at a transistor is above a threshold; and responsive to the rate of change of the drain current being above the threshold, adjust the first logic circuit output or the second logic circuit output to change the count value.
19. The device of claim 16 , wherein the logic circuit is configured to:
detect whether a signal indicative of a rate of change of a drain current at a transistor is above first and second thresholds;
responsive to the signal being above the first and second thresholds, adjust the first logic circuit output or the second logic circuit output to increment the count value;
responsive to the signal being below the first and second thresholds, adjust the first logic circuit output or the second logic circuit output to decrement the count value; and
responsive to the signal being between the first threshold and the second threshold, maintain the count value.
20. The device of claim 16 , further comprising:
a comparator having a comparator output;
a delay circuit having a delay circuit output; and
a flip-flop having a flip-flop clock input, a data input and a flip-flop output, the flip-flop clock input coupled to the delay circuit output, and the data input coupled to the comparator output.