Dual port SRAM cell and design method thereof

1. An integrated circuit comprising:

a dual port Static Random Access Memory (SRAM) cell including a plurality of transistors;

a bit line pair connected to the dual port SRAM cell, the bit line pair including a first bit line and a second bit line spaced apart from each other in a first direction and extending in a second direction perpendicular to the first direction;

a power line group including a plurality of power lines spaced apart from each other in the first direction, spaced apart from the bit line pair placed in the first direction, and extending in the second direction, the power line group being configured to apply a voltage to the dual-port SRAM cell; and

a first word line provided between the first bit line and the second bit line and connected to the dual port SRAM cell.

2. The integrated circuit of claim 1 , further comprising:

a complementary bit line pair including a first complementary bit line complementary to the first bit line and a second complementary bit line complementary to the second bit line, the complementary bit line pair being spaced apart from the bit line pair in the first direction, and connected to the dual port SRAM cell; and

a second word line provided between the first complementary bit line and the second complementary bit line and connected to the dual port SRAM cell,

wherein the power line group is provided between the bit line pair and the complementary bit line pair.

3. The integrated circuit of claim 1 , wherein each of the plurality of power lines is configured to apply a power supply voltage or a ground voltage to the dual port SRAM cell.

4. The integrated circuit of claim 1 , further comprising a dummy line provided between the bit line pair and the power line group and electrically independent from the dual port SRAM cell.

5. The integrated circuit of claim 1 , wherein the bit line pair, the power line group, and the first word line are formed on a same wiring layer.

6. The integrated circuit of claim 1 , further comprising:

a metal wiring extending in the first direction and traversing the bit line pair and the power line group on the bit line pair and the power line group; and

a via connecting the first word line to the metal wiring.

7. The integrated circuit of claim 1 , wherein the plurality of transistors comprise a gate-all-around field-effect transistor (GAAFET) or a FinFET.

8. An integrated circuit comprising:

a first bit cell and a second bit cell adjacent to the first bit cell in a first direction;

a boundary dummy line extending in a second direction perpendicular to the first direction at a boundary between the first bit cell and the second bit cell and electrically independent from the first bit cell and the second bit cell;

a first bit line pair connected to the first bit cell, the first bit line pair including a first bit line and a second bit line extending in the second direction and spaced apart from each other in the first direction;

a first complementary bit line pair spaced apart from the first bit line pair in the first direction and connected to the first bit cell, the first complementary bit line pair including a first complementary bit line complementary to the first bit line and a second complementary bit line complementary to the second bit line;

a power line group including a plurality of power lines provided between the first bit line pair and the first complementary bit line pair and spaced apart from the first bit line pair in the first direction, the power line group being configured to apply a voltage to the first bit cell;

a first word line provided between the first bit line and the second bit line and connected to the first bit cell; and

a second word line provided between the first complementary bit line and the second complementary bit line and connected to the first bit cell.

9. The integrated circuit of claim 8 , further comprising:

a second bit line pair connected to the second bit cell, the second bit line pair including a third bit line and a fourth bit line extending in the second direction and spaced apart from each other in the first direction; and

a third word line provided between the third bit line and the fourth bit line and connected to the second bit cell,

wherein the boundary dummy line is provided between the first complementary bit line pair and the second bit line pair.

10. The integrated circuit of claim 8 , further comprising at least one dummy line provided in at least one of between the first bit line pair and the power line group and between the first complementary bit line pair and the power line group, and electrically independent from the first bit cell.

11. The integrated circuit of claim 10 , wherein a power supply voltage or a ground voltage is applied to the at least one dummy line.

12. The integrated circuit of claim 8 , wherein the boundary dummy line, the first bit line pair, the first complementary bit line pair, the power line group, the first word line, and the second word line are formed on a same wiring layer.

13. The integrated circuit of claim 8 , further comprising:

a metal wiring extending in the first direction and traversing the first bit line pair and the first complementary bit line pair on the first bit line pair and the first complementary bit line pair; and

a via connecting the first word line to the metal wiring.

14. The integrated circuit of claim 8 , wherein the first bit cell and the second bit cell comprise dual port Static Random Access Memory (SRAM) cells.

15. An integrated circuit design method comprising:

forming a first bit cell;

forming, on the first bit cell, a first bit line pair including a first bit line and a second bit line spaced apart from each other in a first direction and extending in a second direction perpendicular to the first direction;

forming, on the first bit cell, a first complementary bit line pair including a first complementary bit line and a second complementary bit line spaced apart from each other in the first direction and extending in the second direction; and

forming, on the first bit cell, a first word line between the first bit line and the second bit line and a second word line between the first complementary bit line and the second complementary bit line.

16. The method of claim 15 , further comprising forming a power line group including a plurality of power lines between the first bit line pair and the first complementary bit line pair.

17. The method of claim 16 , further comprising forming at least one dummy line electrically independent from the first bit cell in at least one of between the first bit line pair and the power line group and between the first complementary bit line pair and the power line group.

18. The method of claim 17 , wherein a power voltage or a ground voltage is applied to the at least one dummy line.

19. The method of claim 15 , further comprising:

forming a second bit cell adjacent to the first bit cell in the first direction; and

forming a boundary dummy line extending in the second direction at a boundary between the first bit cell and the second bit cell,

wherein the boundary dummy line is electrically independent from the first bit cell and the second bit cell.

20. The method of claim 15 , wherein the forming of the first bit line pair, the forming of the first complementary bit line pair, and the forming of the first word line and the second word line are performed in parallel with each other.