IP Library Granted Patent US 11,832,502
Granted Patent B2
US 11,832,502 · App. 17/700,376 · Granted Nov 28, 2023

Display device including dummy pixels in a non-display area

Inventors: Junyong An (Yongin-si, KR); Hyunae Park (Yongin-si, KR); Hyungjun Park (Yongin-si, KR); Seungwoo Sung (Yongin-si, KR); Youngsoo Yoon (Yongin-si, KR); Ilgoo Youn (Yongin-si, KR); Jieun Lee (Yongin-si, KR); Yunkyeong In (Yongin-si, KR); Donghyeon Jang (Yongin-si, KR); Junyoung Jo (Yongin-si, KR)
Assignee: Samsung Display Co., Ltd.
H10K59/88H10K59/122H10K59/1213H10K59/1216H10K59/131
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Quick Facts
Patent No.
US 11,832,502
App. No.
17/700,376
Granted
Nov 28, 2023
Kind
B2
Abstract

A display panel includes a substrate including a first region, a second region, a non-display area that surrounds the first region and the second region, and a display area that surrounds the non-display area; a plurality of pixels arranged on the display area; a plurality of dummy pixels arranged on the non-display area and emitting no light; and a plurality of signal lines configured to electrically connect the plurality of pixels to the plurality of dummy pixels. Some of the plurality of dummy pixels are arranged between the first region and the second region.

Claims (21)

1. A display panel comprising:

a substrate including a first region, a second region, a non-display area that surrounds the first region and the second region, and a display area that surrounds the non-display area;

a plurality of pixels arranged on the display area;

a plurality of dummy pixels arranged on the non-display area and emitting no light, the plurality of dummy pixels includes a first dummy pixel and a second dummy pixel;

a first signal line connecting to the first dummy pixel and extending in a first direction;

a second signal line connecting to the second dummy pixel and spaced apart from the first signal line in a second direction crossing the first direction;

a connection wire connecting the first signal line and the second signal line; and

a detouring line connecting to the connection wire, the detouring line detouring around the first region.

2. The display panel of claim 1 , wherein the detouring line is integrally provided with the first signal line or the second signal line.

3. The display panel of claim 1 , wherein at least one edge of the first signal line or the second signal line is disposed in the non-display area.

4. The display panel of claim 1 , wherein the first signal line is a scan line connecting the first dummy pixel, and the second signal line is a previous scan line connecting the second dummy pixel.

5. The display panel of claim 1 , wherein the first signal line is a light-emission control line connecting the first dummy pixel, and the second signal line is a light-emission control line connecting the second dummy pixel.

6. The display panel of claim 1 , wherein the first signal line and the second signal line are arranged on a same layer, and the connection wire is arranged on a layer different from the first signal line and the second signal line.

7. The display panel of claim 1 , wherein the plurality of dummy pixels are arranged to surround the first region and the second region.

8. The display panel of claim 1 , wherein

each of the plurality of pixels comprises a pixel circuit and a display element, the pixel circuit comprising at least one transistor and the display element being connected to the pixel circuit, each of the plurality of dummy pixels comprises a dummy pixel circuit comprising at least one dummy transistor, and a structure of the pixel circuit is a same structure as a structure of the dummy pixel circuit.

9. The display panel of claim 1 , further comprising a plurality of initializing voltage lines spaced apart from each other around the first region and the second region, wherein the plurality of initializing voltage lines are connected to each other via an initializing electrode layer in a ring shape that surrounds the first region and the second region.

10. The display panel of claim 1 , wherein the initializing electrode layer is arranged on a different layer than a layer on which the plurality of initializing voltage lines are arranged and is connected to the plurality of initializing voltage lines via contact holes.

11. The display panel of claim 1 , wherein further comprising data lines each extending in the second direction and each being cut around the first region, and respective two cut portions of the cut data lines are connected to each other by data connection lines that detour around the first region.

12. The display panel of claim 11 , wherein some of the data connection lines are arranged on a same layer on which the data lines are arranged and are connected to each other via bridge metals arranged on a different layer than a layer on which the data lines are arranged.

13. The display panel of claim 11 , wherein the data connection lines comprise lower data connection lines arranged on a same layer on which the data lines are arranged, and upper data connection lines arranged on a different layer than the layer on which the data lines are arranged, and the lower data connection lines and the upper data connection lines alternate with each other.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 21, 2022
From: AN, JUNYONG; PARK, HYUNAE; PARK, HYUNGJUN; SUNG, SEUNGWOO; YOON, YOUNGSOO; YOUN, ILGOO; LEE, JIEUN; IN, YUNKYEONG; JANG, DONGHYEON; JO, JUNYOUNG
To: SAMSUNG DISPLAY CO., LTD.
Reel/Frame 059330/0362 →
Priority Claims (1)
KR 10-2018-0153024 · Nov 30, 2018 · national
Continuity (2)
Continuation 16698881 · Nov 27, 2019
Related Publication 20220216274A1 · Jul 7, 2022
Cited By (1)
US 12,530,061