Security device and methods of operating a security device
A device includes a safety domain having a processing unit and a memory and is configured to provide at least one functionality and to implement one more safety measures for detecting faults. The safety domain is configured to transmit at least one alarm signal indicating one or more detected errors in response to detecting the faults. The device further includes a security domain having a processing unit and a memory and is configured to provide cryptographic services and to obtain alarm signals. The security domain is configured to perform security-related operations in a secure state in response to obtaining an alarm signal from the safety domain.
1. An integrated processing device comprising:
a security domain comprising at least one processing unit and a memory and configured to provide one or more cryptographic services;
a safety domain coupled to the security domain, the safety domain comprising at least one processing unit and a memory and configured to execute one or more processes, control one or more peripherals, and provide one more safety measures to detect one or more hardware faults, wherein the safety domain operates continuously or substantially continuously according to a safety related standard, further wherein the security domain operates independently of the safety domain;
wherein the safety domain is configured to, in response to detecting a hardware fault in a component of the safety domain,
perform a hardware-related remedial action on one or more components of the safety domain; and
after initiation of the hardware-related remedial action, transmit an alarm signal indicating detection of hardware faults to the security domain; and
wherein the security domain is configured to, in response to the alarm signal, perform one or more cryptographic service-related security operations.
2. The integrated processing device of claim 1 , wherein the security domain is physically separate from the safety domain.
3. The integrated processing device of claim 1 , wherein the one or more cryptographic service-related security operations comprise deleting cryptographic keys stored in the security domain.
4. The integrated processing device of claim 1 , wherein the one or more cryptographic service-related security operations comprise sending out a security interrupt signal.
5. The integrated processing device of claim 1 , wherein the one or more cryptographic service-related security operations comprise resetting one or more settings of the security domain.
6. The integrated processing device of claim 1 , wherein the one or more cryptographic service-related security operations comprise locking one or more external interfaces of the security domain.
7. The integrated processing device of claim 1 , wherein the one or more cryptographic service-related security operations comprise delaying performance of one or more previously scheduled cryptographic service-related actions for at least a predefined period of time.
8. The integrated processing device of claim 1 , further comprising
a first chip comprising the safety domain; and
a second chip comprising the security domain, the second chip being separate from the first chip.
9. The integrated processing device of claim 1 , wherein the safety domain and the security domain are located on a same semiconductor substrate.
10. The integrated processing device of claim 1 , wherein
the integrated processing device is a semiconductor integrated circuit chip comprising a plurality of processor cores,
the safety domain comprises one or more first cores of the plurality of processor cores, and
the security domain comprises one or more second cores of the plurality of processor cores, the first cores being separate from the second cores.
11. The integrated processing device claim 1 , further comprising a communication interface, wherein the communication interface is coupled to the safety domain and to the security domain.
12. The integrated processing device of claim 1 , wherein the safety domain comprises one or more application specific peripherals.
13. The integrated processing device of claim 1 , wherein the security domain comprises at least one cryptographic accelerator or random number generator.
14. The integrated processing device of claim 1 , wherein the safety domain is configured to detect one or more hardware faults by obtaining sensor data and detecting operating condition violations in the safety domain from the obtained sensor data.
15. The integrated processing device of claim 14 , wherein the sensor data comprises sensor data comprises temperature data, supply voltage data, and/or clock data.
16. The integrated processing device of claim 1 , wherein the safety domain is configured to control a motor.
17. The integrated processing device of claim 1 , wherein the safety domain is configured to control one or more brakes of a vehicle.
18. The integrated processing device of claim 1 , is configured to extract data from one or more radar measurements obtained by the integrated processing device.
19. The integrated processing device of claim 1 , wherein the hardware-related remedial action comprises controlling the at least one processing unit of the safety domain to operate in a lockstep mode.
20. A security domain system configured to provide one or more cryptographic services, comprising:
a memory; and
at least one processing unit configured to
receive an alarm signal from a safety domain system that detects hardware faults and operates continuously or substantially continuously according to a safety related standard, the alarm signal indicative of the safety domain system initiating remedial action in response to a hardware fault occurring in the safety domain system, wherein the security domain system operates independently of the safety domain system, and
in response to the alarm signal, perform one or more cryptographic service-related operations in at least one secure state.
21. The security domain system of claim 20 , wherein the one or more cryptographic service-related operations comprise deleting cryptographic keys stored in the security domain system.
22. The security domain system of claim 20 , wherein the one or more cryptographic service-related operations comprise sending out a security interrupt signal.
23. The security domain system of claim 20 , wherein the one or more cryptographic service-related operations comprise resetting one or more settings of the security domain system.
24. The security domain system of claim 20 , wherein the one or more cryptographic service-related operations comprise locking one or more external interfaces of the security domain system.
25. An integrated processing device comprising:
a security domain comprising at least one processing unit and a memory and configured to provide one or more cryptographic services;
a safety domain coupled to the security domain, the safety domain comprising at least one processing unit and a memory and configured to execute one or more processes, control one or more peripherals, and provide one more safety measures to detect one or more hardware faults, wherein the safety domain operates continuously or substantially continuously according to a safety related standard, further wherein the security domain is physically separate from the safety domain;
wherein the safety domain is configured to, in response to detecting a hardware fault in a component of the safety domain,
perform a hardware-related remedial action on one or more components of the safety domain; and
after initiation of the hardware-related remedial action, transmit an alarm signal indicating detection of hardware faults to the security domain; and
wherein the security domain is configured to, in response to the alarm signal, perform one or more cryptographic service-related security operations.