Wafer level electron beam prober
Wafer level electron beam prober systems, devices, and techniques, are described herein related to providing wafer level testing for fabricated device structures. Such wafer level testing contacts a first side of a die of a wafer with a probe to provide test signals to the die under test and performs e-beam imaging of the first side of the die while the test signals are provided to the die under test.
1 . A system, comprising:
a wafer stage to receive a wafer comprising at least one die and to position the die for testing;
a probe to contact a first region of a first side of the die and to provide a test signal to the first region of the first side of the die, wherein the probe comprises a probe card comprising a plurality of probe tips to contact pads of the first side of the die, and wherein the probe tips are adjacent a perimeter of the probe card and the probe card comprises a translucent or transparent region in an interior of the probe card at least partially surrounded by the perimeter;
an electron-beam (e-beam) column to provide an e-beam to a second region of the first side of the die;
a detector to detect an e-beam signal from the second region of the first side of the die; and
a processor circuit to generate test data based on the e-beam signal.
2 . The system of claim 1 , wherein the translucent or transparent region comprises an open region of the interior of the probe card.
3 . The system of claim 1 , further comprising:
a chamber and a vacuum pump to pull a vacuum in the chamber comprising the die during test, wherein at least portions of the wafer stage, the probe, and the e-beam column are within the chamber.
4 . The system of claim 3 , wherein the wafer stage is to position a second die of the wafer for testing while a continued vacuum is maintained during testing of the die and the second die.
5 . The system of claim 4 , wherein the probe is to provide a second test signal to the second die during testing of the second die, and wherein the test signal provides a first test type and the second test signal provides a second test type other than the first test type.
6 . The system of claim 1 , wherein the first region comprises a semiconductor material or the first region comprises a metallization layer of an integrated circuit, the metallization layer comprising one of a first or second metal layer directly over a transistor contact layer.
7 . The system of claim 1 , wherein the processor circuit is to perform, based on the test signal and the e-beam signal, at least one of e-beam signal image mapping, e-beam logic state imaging, optical-electrical fault mapping, e-beam device perturbation, or stroboscopic e-beam signal image mapping.
8 . A method, comprising:
receiving a wafer comprising at least one die for testing;
contacting a first region of a first side of the die, wherein contacting the first region comprises contacting the first region with a probe card, the probe card comprising a plurality of probe tips adjacent a perimeter of the probe card and a translucent or transparent region in an interior of the probe card at least partially surrounded by the perimeter;
providing a test signal to the first region of the first side the die;
emitting an electron-beam (e-beam) on a second region of the first side of the die; and
receiving an e-beam signal from the second region of the first side of the die.
9 . The method of claim 8 , further comprising:
pulling a vacuum within a chamber comprising the wafer prior to said emitting the e-beam;
positioning, during said pulling the vacuum, a second die of the wafer for testing;
providing or receiving, during said pulling the vacuum, a second test signal to the second die; and
emitting, during said pulling the vacuum and said providing the second test signal, a second e-beam on the second die.
10 . The method of claim 9 , wherein the test signal provides a first test type and the second test signal provides a second test type other than the first test type.
11 . The method of claim 8 , wherein the first region of the die comprises a metallization layer of an integrated circuit, the metallization layer comprising one of a first or second metal layer directly over a transistor contact layer of the integrated circuit.
12 . The method of claim 8 , further comprising:
performing, based on test data corresponding to the e-beam signal, at least one of e-beam signal image mapping, e-beam logic state imaging, optical-electrical fault mapping, e-beam device perturbation, or stroboscopic e-beam signal image mapping.
13 . A method, comprising:
pulling a vacuum in a chamber surrounding a wafer, the wafer comprising a plurality of dies for testing;
positioning a first of the plurality of dies for testing of the first die; and
during said pulling the vacuum in the chamber:
providing a first test signal to a first region of a first side of the first die;
attaining a first electron-beam (e-beam) signal from a second region of the first side of the first die during said providing the first test signal;
positioning a second of the plurality of dies for testing of the second die;
providing a second test signal to a first region of a first side of the second die; and
attaining a second e-beam signal from a second region of the first side of the second die during said providing the second test signal.
14 . The method of claim 13 , wherein the first test signal provides a first test type and the second test signal provides a second test type other than the first test type.
15 . The method of claim 13 , wherein providing the first test signal to the first region comprises contacting the first region with a probe card.
16 . The method of claim 15 , wherein the probe card comprises a plurality of probe tips adjacent a perimeter of the probe card and a translucent or transparent region in an interior of the probe card at least partially surrounded by the perimeter.
17 . The method of claim 13 , wherein the first region of the first die comprises a metallization layer of an integrated circuit, the metallization layer comprising one of a first or second metal layer directly over a transistor contact layer of the integrated circuit.
18 . The method of claim 13 , further comprising:
performing, based on test data corresponding to the first or second e-beams, at least one of e-beam signal image mapping, e-beam logic state imaging, optical-electrical fault mapping, e-beam device perturbation, or stroboscopic e-beam signal image mapping.
19 . A system, comprising:
a wafer stage to receive a wafer comprising a first die and a second die, and to position the first die for testing;
a probe to contact a first region of a first side of the first die and to provide a test signal to the first region of the first side of the first die;
an electron-beam (e-beam) column to provide an e-beam to a second region of the first side of the first die;
a detector to detect an e-beam signal from the second region of the first side of the first die;
a chamber and a vacuum pump to pull a vacuum in the chamber comprising the first die during test, wherein at least portions of the wafer stage, the probe, and the e-beam column are within the chamber, and wherein the wafer stage is to position the second die of the wafer for testing while a continued vacuum is maintained during testing of the first die and the second die; and
a processor circuit to generate test data based on the e-beam signal.
20 . The system of claim 19 , wherein the probe comprises a probe card comprising a plurality of probe tips to contact pads of the first side of the first die.
21 . The system of claim 19 , wherein the probe is to provide a second test signal to the second die during testing of the second die, and wherein the test signal provides a first test type and the second test signal provides a second test type other than the first test type.
22 . The system of claim 19 , wherein the first region comprises a semiconductor material or the first region comprises a metallization layer of an integrated circuit, the metallization layer comprising one of a first or second metal layer directly over a transistor contact layer.
23 . The system of claim 19 , wherein the processor circuit is to perform, based on the test signal and the e-beam signal, at least one of e-beam signal image mapping, e-beam logic state imaging, optical-electrical fault mapping, e-beam device perturbation, or stroboscopic e-beam signal image mapping.