IP Library Granted Patent US 12,424,495
Granted Patent B2
US 12,424,495 · App. 17/701,771 · Granted Sep 23, 2025

Chip separation supported by back side trench and adhesive therein

Inventors: Gunther Mackh (Neumarkt, DE); Martin Brandl (Brennburg, DE)
Assignee: Infineon Technologies AG
H01L21/78H01L21/6836H01L21/68742
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Quick Facts
Patent No.
US 12,424,495
App. No.
17/701,771
Granted
Sep 23, 2025
Kind
B2
Abstract

A method of separating an electronic chip from a wafer is disclosed. In one aspect, the method comprises forming at least one trench in a back side of the wafer around at least part of the electronic chip to be separated, forming a back side metallization covering at least part of the back side and at least part of the at least one trench and attaching an adhesive layer of a tape to at least part of the back side metallization. The electronic chip is separated by removing material from a front side of the wafer along a separation path which includes part of the at least one trench in such a way that, during separating, the adhesive layer fills at least part of the at least one trench above a level of the back side metallization on the back side.

Claims (26)

1. A method of separating an electronic chip from a wafer, wherein the method comprises:

forming two spaced trenches in a back side of the wafer around at least part of the electronic chip to be separated;

forming a back side metallization covering at least part of the back side and at least part of the at least one trench;

attaching an adhesive layer of a tape to at least part of the back side metallization; and

separating the electronic chip by removing material from a front side of the wafer along a separation path which includes part of each of the two spaced trenches in such a way that, during separating, the adhesive layer fills at least part of the two spaced trenches above a level of the back side metallization on the back side to support the back side metallization along the separation path during the separating of the electronic chip.

2. The method according to claim 1 , wherein the method comprises forming the two spaced trenches parallel to each other and/or around a common center.

3. The method according to claim 1 , wherein the method comprises separating the electronic chip along the separation path which includes a region extending between the two spaced trenches.

4. The method according to claim 1 , wherein the method comprises forming the two spaced trenches circumferentially closed around the entire electronic chip to be separated.

5. The method according to claim 1 , wherein the method comprises forming the two spaced trenches with a depth being smaller than or equal to a thickness of the adhesive layer.

6. The method according to claim 1 , wherein the method comprises forming the two spaced trenches with a depth in a range from 3 μm to 10 μm.

7. The method according to claim 1 , wherein the method comprises forming each of the two spaced trenches with a width smaller than a width of the separation path.

8. The method according to claim 1 , wherein the method comprises separating the electronic chip by one of the group consisting of cutting with a mechanical blade, and laser processing.

9. The method according to claim 8 , wherein the method comprises separating the electronic chip by guiding the mechanical blade through the entire wafer, through the entire adhesive layer, and into a foil of the tape below the adhesive layer.

10. The method according to claim 1 , wherein the method comprises separating the electronic chip in such a way that the adhesive layer fills the entire two spaced trenches during separating.

11. The method according to claim 1 , wherein the method comprises forming the two spaced trenches by covering the back side of the wafer with a patterned mask, and by etching the wafer through the patterned mask.

12. The method according to claim 1 , wherein the method comprises picking the separated electronic chip from the tape after the separating.

13. The method according to claim 12 , wherein picking the separated electronic chip comprises lifting the electronic chip from the tape by at least one pin applying a lifting force to the back side of the electronic chip.

14. The method according to claim 12 , wherein picking the separated electronic chip comprises sucking the lifted electronic chip at the front side of the electronic chip.

15. The method according to claim 1 , wherein the electronic chip has a thickness of less than 60 μm.

16. The method according to claim 1 , wherein the electronic chip is configured for experiencing a vertical current flow between the front side and the back side during operation.

17. A method of separating an electronic chip from a wafer, wherein the method comprises:

forming two spaced trenches in a back side of the wafer around at least part of the electronic chip to be separated;

forming a back side metallization covering at least part of the back side and at least part of the at least one trench;

attaching an adhesive layer of a tape to at least part of the back side metallization;

separating the electronic chip by removing material from a front side of the wafer along a separation path which includes part of each of the two spaced trenches in such a way that, during separating, the adhesive layer fills at least part of the two spaced trenches above a level of the back side metallization on the back side to support the back side; and

wherein the method comprises forming the two spaced trenches by covering the back side of the wafer with a patterned mask, by doping the wafer through the patterned mask, and by etching the wafer after removing the patterned mask.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 24, 2022
From: MACKH, GUNTHER; BRANDL, MARTIN
To: INFINEON TECHNOLOGIES AG
Reel/Frame 059390/0832 →
Priority Claims (1)
DE 10 2021 109 003.2 · Apr 12, 2021 · national
Continuity (1)
Related Publication 20220328355A1 · Oct 13, 2022
References Cited (23)
US 5541140A · Goebel et al. · 1996 [cited by applicant]
US 6368932B1 · Goebel et al. · 2002 [cited by applicant]
US 6720667B2 · Kim · 2004 [cited by examiner]
US 8673700B2 · Yedinak et al. · 2014 [cited by applicant]
US 20050006725A1 · Kurosawa · 2005 [cited by examiner]
US 20050009299A1 · Wada · 2005 [cited by examiner]
US 20060054273A1 · Nagasaka · 2006 [cited by examiner]
US 20060223234A1 · Terayama · 2006 [cited by examiner]
US 20080277765A1 · Lane · 2008 [cited by examiner]
US 20110006404A1 · Lee · 2011 [cited by examiner]
US 20110062564A1 · Gruenhagen et al. · 2011 [cited by applicant]
US 20110277813A1 · Rogers et al. · 2011 [cited by applicant]
US 20120313224A1 · Fukuda et al. · 2012 [cited by applicant]
US 20130189830A1 · Hirschler · 2013 [cited by examiner]
US 20150249133A1 · Yanase et al. · 2015 [cited by applicant]
US 20160042997A1 · Takahashi · 2016 [cited by examiner]
US 20170148697A1 · Kamphuis · 2017 [cited by examiner]
US 20180166328A1 · Tang · 2018 [cited by examiner]
US 20220013401A1 · Wirz · 2022 [cited by examiner]
DE 4320780 · 1995 [cited by applicant]
DE 102016118477 · 2018 [cited by applicant]
EP 1050076 · 2000 [cited by applicant]
Charavel, Remy, et al. “Tuning of Etching Rate by Implantation: Silicon, Polysilicon and Oxide”, American Institute of Physics, Nov. 2006. [cited by applicant]