IP Library Granted Patent US 8,598,688
Granted Patent B2
US 8,598,688 · App. 13/157,746 · Granted Dec 3, 2013

Semiconductor device

Inventors: Kyohei Fukuda (Matsumoto, JP); Eiji Mochizuki (Matsumoto, JP); Mitsutoshi Sawano (Matsumoto, JP); Takaaki Suzawa (Matsumoto, JP)
Assignee: Fuji Electric Co., Ltd.
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Quick Facts
Patent No.
US 8,598,688
App. No.
13/157,746
Granted
Dec 3, 2013
Kind
B2
Abstract

A semiconductor device and manufacturing method are disclosed which prevent breakage and chipping of a semiconductor chip and improve device characteristics. A separation layer is in a side surface of an element end portion of the chip. An eave portion is formed by a depressed portion in the element end portion. A collector layer on the rear surface of the chip extends to a side wall and bottom surface of the depressed portion, and is connected to the separation layer. A collector electrode is over the whole surface of the collector layer, and is on the side wall of the depressed portion. The thickness of an outermost electrode film is 0.05 μm or less. The collector electrode on the rear surface of the chip is joined onto an insulating substrate via a solder layer, which covers the collector electrode on a flat portion of the rear surface of the semiconductor chip.

Claims (29)

1. A semiconductor device, comprising:

a front surface element structure provided on a first main surface of a first conductivity type substrate;

a second conductivity type first semiconductor region provided in an element end portion of the first main surface of the substrate;

a depressed portion reaching the first semiconductor region from a second main surface of the substrate;

a second conductivity type second semiconductor region electrically connected to the first semiconductor region provided on the second main surface of the substrate;

and

an electrode formed from an electrode film of at least more than one layer provided over the whole surface of the second semiconductor region,

wherein the thickness of the outermost electrode film of the electrode provided on a side wall of the depressed portion is 0.05 μm or less.

2. The semiconductor device according to claim 1 , wherein the thickness of the outermost electrode film of the electrode provided on a bottom surface of the depressed portion is 0.05 μm or less.

3. The semiconductor device according to claim 1 , further comprising a solder layer covering the electrode other than portions of the electrode which are provided on the side wall and bottom surface of the depressed portion.

4. The semiconductor device according to claim 3 , wherein the solder layer further covers the electrode provided on an open end portion of the depressed portion.

5. A semiconductor device, comprising:

a front surface element structure provided on a first main surface of a first conductivity type substrate;

a second conductivity type first semiconductor region provided in an element end portion of the first main surface of the substrate;

a depressed portion reaching the first semiconductor region from a second main surface of the substrate;

a second conductivity type second semiconductor region electrically connected to the first semiconductor region provided on the second main surface of the substrate;

and

an electrode in contact with the second semiconductor region provided extending from an element central portion of the second main surface of the substrate to a side wall of the depressed portion.

6. A semiconductor device, comprising:

a front surface element structure provided on a first main surface of a first conductivity type substrate;

a second conductivity type first semiconductor region provided in an element end portion of the first main surface of the substrate;

a depressed portion reaching the first semiconductor region from a second main surface of the substrate;

a second conductivity type second semiconductor region electrically connected to the first semiconductor region provided on the second main surface of the substrate;

and

an electrode provided over the whole surface of the second semiconductor region,

wherein the electrode provided on a side wall and bottom surface of the depressed portion is covered with a film formed from a material with poor solder wettability.

7. The semiconductor device according to claim 6 , wherein the film formed from a material with poor solder wettability covers only the electrode provided on the bottom surface of the depressed portion.

8. The semiconductor device according to claim 6 , wherein the film formed from a material with poor solder wettability is a polyimide resin film.

9. The semiconductor device according to claim 5 , further comprising a solder layer covering the electrode exposed on the second main surface side of the substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 23, 2011
From: FUKUDA, KYOHEI; MOCHIZUKI, EIJI; SAWANO, MITSUTOSHI; SUZAWA, TAKAAKI
To: FUJI ELECTRIC CO., LTD.
Reel/Frame 026791/0963 →
Priority Claims (1)
JP 2010-133365 · Jun 10, 2010 · national
Continuity (1)
Related Publication 20120313224A1 · Dec 13, 2012