Generating a reduced block model view on-the-fly
A word-level design model may be loaded into memory. Next, a masking layer may be created which includes objects in the word-level design model that are not used by an IC design analysis system. The masking layer may then be used to provide a reduced block model view on-the-fly to the IC design analysis system.
1. A method, comprising:
loading a word-level design model representing an integrated circuit (IC) design into a memory;
creating, by a processor, a set of masking layers, wherein each masking layer in the set of masking layers includes objects in the word-level design model that are not used by a corresponding IC design analysis system in a set of IC design analysis systems; and
using a respective masking layer in the set of masking layers to provide a respective reduced block model view on-the-fly to a respective IC design analysis system.
2. The method of claim 1 , wherein using the respective masking layer to provide the respective reduced block model view on-the-fly to the respective IC design analysis system comprises:
receiving a request for connectivity information in the word-level design model from the respective IC design analysis system;
determining the connectivity information based on the word-level design model and the respective masking layer; and
providing the connectivity information to the respective IC design analysis system.
3. The method of claim 1 , wherein creating the respective masking layer which includes objects in the word-level design model that are not used by the respective IC design analysis system comprises:
identifying a subset of objects in the word-level design model by performing word-level traversals from input and output ports; and
adding objects that are not in the subset of objects to the respective masking layer.
4. The method of claim 3 , wherein identifying the subset of objects in the word-level design model by performing word-level traversals from input and output ports comprises identifying objects in a path from a port to a first level sequential register.
5. The method of claim 3 , wherein identifying the subset of objects in the word-level design model by performing word-level traversals from input and output ports comprises:
selecting a first port connected to a first clock domain crossing (CDC) synchronization circuit;
selecting a second port connected to a second CDC synchronization circuit; and
identifying objects in a first path from the first port and a second path from the second port that converge at a sequential register.
6. The method of claim 3 , wherein identifying the subset of objects in the word-level design model by performing word-level traversals from input and output ports comprises:
identifying objects in different blocks of the word-level design model in parallel; and
aggregating the objects identified in the different blocks of the word-level design model to obtain the subset of objects.
7. The method of claim 6 , wherein the IC design is a system on a chip (SoC) design, wherein the respective reduced block model view corresponds to a top-level view in the SoC design, and wherein the different blocks of the word-level design model correspond to different blocks in the top-level view of the SoC design.
8. The method of claim 1 , wherein the set of IC design analysis systems includes a clock-domain-crossing (CDC) analysis system, a reset-domain-crossing (RDC) analysis system, a low-power (LP) analysis system, or a structural analysis system.
9. A non-transitory computer readable storage medium storing instructions, which when executed by a processor, cause the processor to:
load a word-level design model representing an integrated circuit (IC) design into a memory;
create a masking layer which includes objects in the word-level design model that are not used by an IC design analysis system, wherein the IC design analysis system is a reset-domain-crossing (RDC) analysis system or a low-power (LP) analysis system, wherein creating the masking layer which includes objects in the word-level design model that are not used by the IC design analysis system comprises:
identifying a subset of objects in the word-level design model by performing word-level traversals from input and output ports; and
adding objects that are not in the subset of objects to the masking layer; and
use the masking layer to provide a reduced block model view on-the-fly to the IC design analysis system.
10. The non-transitory computer readable storage medium of claim 9 , wherein using the masking layer to provide the reduced block model view on-the-fly to the IC design analysis system comprises:
receiving a request for connectivity information in the word-level design model from the IC design analysis system;
determining the connectivity information based on the word-level design model and the masking layer; and
providing the connectivity information to the IC design analysis system.
11. The non-transitory computer readable storage medium of claim 9 , wherein identifying the subset of objects in the word-level design model by performing word-level traversals from input and output ports comprises identifying objects in a path from a port to a first level sequential register.
12. The non-transitory computer readable storage medium of claim 9 , wherein identifying the subset of objects in the word-level design model by performing word-level traversals from input and output ports comprises:
identifying objects in different blocks of the word-level design model in parallel; and
aggregating the objects identified in the different blocks of the word-level design model to obtain the subset of objects.
13. The non-transitory computer readable storage medium of claim 9 , wherein creating the masking layer comprises adding a reset signal to the masking layer that does not cross a clock domain boundary.
14. The non-transitory computer readable storage medium of claim 9 , wherein creating the masking layer comprises adding logic gates to the masking layer which are not used for determining a power mode of the IC design.
15. An apparatus, comprising:
a memory storing instructions; and
a processor, coupled with the memory and to execute the instructions, the instructions when executed causing the processor to:
load a word-level design model representing an integrated circuit (IC) design into the memory;
create a masking layer which includes objects in the word-level design model that are not used by an IC design analysis system, wherein creating the masking layer comprises:
identifying a subset of objects in the word-level design model by performing word-level traversals from input and output ports, wherein performing word-level traversals includes determining connectivity for multiple bits of a word using a single word-level traversal operation; and
adding objects that are not in the subset of objects to the masking layer;
receive a request for connectivity information in the word-level design model from the IC design analysis system;
determine the connectivity information based on the word-level design model and the masking layer; and
provide the connectivity information to the IC design analysis system.
16. The apparatus of claim 15 , wherein identifying the subset of objects in the word-level design model by performing word-level traversals from input and output ports comprises identifying objects in a path from a port to a first level sequential register.
17. The apparatus of claim 15 , wherein identifying the subset of objects in the word-level design model by performing word-level traversals from input and output ports comprises:
selecting a first port connected to a first clock domain crossing (CDC) synchronization circuit;
selecting a second port connected to a second CDC synchronization circuit; and
identifying objects in a first path from the first port and a second path from the second port that converge at a sequential register.
18. The apparatus of claim 15 , wherein identifying the subset of objects in the word-level design model by performing word-level traversals from input and output ports comprises:
identifying objects in different blocks of the word-level design model in parallel; and
aggregating the objects identified in the different blocks of the word-level design model to obtain the subset of objects.
19. The apparatus of claim 15 , wherein the IC design analysis system is a clock-domain-crossing (CDC) analysis system, a reset-domain-crossing (RDC) analysis system, a low-power (LP) analysis system, or a structural analysis system.