Sequential data optimized sub-regions in storage devices

1. A storage system comprising:

a memory array;

a random access memory configured to store at least a portion of one or more logical-to-physical (L2P) mapping tables; and

a memory controller including processing circuitry including one or more processors, wherein the memory controller is configured to perform operations including:

partitioning the memory array into multiple portions having non-overlapping logical block addressing (LBA) ranges;

assigning performance levels to multiple mapping table entries respectively corresponding to the multiple portions of the memory array based on usage designations for the multiple portions, where a first at least one of the performance levels is not equal to a second at least one of the performance levels;

storing at least a portion of the multiple mapping table entries in the random access memory.

2. The system of claim 1 , wherein partitioning the memory array into the multiple portions includes partitioning the memory array at startup or during runtime.

3. The system of claim 1 , wherein partitioning the memory array into the multiple portions includes partitioning the memory array at startup and re-partitioning the memory array during runtime.

4. The system of claim 1 , wherein partitioning the memory array comprises establishing memory regions having respective granularities of LBA partitioning in the memory array, each region having LBA addresses mapped to a respective different number of physical memory addresses.

5. The system of claim 4 , wherein the memory controller is further configured to perform operations including:

storing data indicative of the performance levels in a region lookup table identifying the memory regions having the respective granularities in the memory array.

6. The system of claim 1 , wherein at least two of the multiple portions are different memory types.

7. The system of claim 1 , wherein a third at least one of the performance levels is not equal to the first at least one of the performance levels and the second at least one of the performance levels.

8. The system of claim 1 , wherein the performance levels include at least one of a read performance level or a write performance level.

9. A method comprising:

partitioning, by a memory controller, a memory array into multiple portions having non- overlapping logical block addressing (LBA) ranges;

assigning, by the memory controller, performance levels to multiple mapping table entries respectively corresponding to the multiple portions of the memory array based on usage designations for the multiple portions, where a first at least one of the performance levels is greater than a second at least one of the performance levels;

and

storing, by the memory controller, at least a portion of the multiple mapping table entries in a random access memory.

10. The method of claim 9 , wherein the partitioning the memory array into the multiple portions includes partitioning the memory array at startup or during runtime.

11. The method of claim 9 , wherein partitioning the memory array into the multiple portions includes partitioning the memory array at startup and re-partitioning the memory array during runtime.

12. The method of claim 9 , wherein partitioning the memory array comprises establishing memory regions having respective granularities of LBA partitioning in the memory array, each region having LBA addresses mapped to a respective different number of physical memory addresses.

13. The method of claim 12 , further comprising:

storing data indicative of the performance levels in a region lookup table identifying the memory regions having the respective granularities in the memory array.

14. The method of claim 9 , wherein at least two of the multiple portions are different memory types.

15. A non-transitory computer readable medium comprising instructions thereon that, when executed by a processor, cause the processor to perform operations comprising:

partitioning a memory array into multiple portions having non-overlapping logical block addressing (LBA) ranges;

assigning performance levels to multiple mapping table entries respectively corresponding to the multiple portions of the memory array based on usage designations for the multiple portions, where a first at least one of the performance levels is greater than a second at least one of the performance levels;

and

storing at least a portion of the multiple mapping table entries in a random access memory.

16. The computer readable medium of claim 15 , wherein partitioning the memory array into the multiple portions includes partitioning the memory array at startup or during runtime.

17. The computer readable medium of claim 15 , wherein partitioning the memory into the multiple portions includes partitioning the memory array at startup and re-partitioning the memory array during runtime.

18. The computer readable medium of claim 15 , wherein partitioning the memory array comprises establishing memory regions having respective granularities of LBA partitioning in the memory array, each region having LBA addresses mapped to a respective different number of physical memory addresses.

19. The computer readable medium of claim 18 , further comprising instructions thereon that, when executed by the processor, cause the processor to perform operations comprising:

storing data indicative of the performance levels in a region lookup table identifying the memory regions having the respective granularities in the memory array.

20. The computer readable medium of claim 15 , wherein at least two of the multiple portions are different memory types.