Power loss protection in memory sub-systems
Aspects of the present disclosure provide systems and methods for improved power loss protection in a memory sub-system of a device. In particular, a power loss protection component allocates a portion of the memory sub-system to non-volatile memory. Responsive to detecting a trigger event at the device, wherein the trigger event may include asynchronous power loss of the device, the power loss protection component detects data written to a volatile cache of the memory sub-system, retrieves the data from the volatile cache, and writes the data to the portion of the memory sub-system allocated to the non-volatile memory.
1. A system comprising:
a plurality of memory components comprising non-volatile memory components and a volatile cache; and
a processing device, operatively coupled with the plurality of memory components, configured to perform operations comprising:
detecting a power loss at a device associated with the plurality of memory components;
identifying data written to the volatile cache;
administering a performance test upon the non-volatile memory components, the performance test including a latency test;
identifying a portion of the non-volatile memory components based on the performance test;
accessing the data written to the volatile cache responsive to the power loss; and
moving the data to the portion of the non-volatile memory components.
2. The system of claim 1 , wherein the identifying the portion of the non-volatile memory components based on the performance test performed upon the portion of the non-volatile memory components further comprises:
performing the performance test upon the non-volatile memory components at a predefined interval; and
identifying the portion of the non-volatile memory components based on the performance test.
3. The system of claim 1 , wherein the identifying the portion of the non-volatile memory components based on the performance test further comprises:
determining a ranking of the portion of the non-volatile memory components based on a performance metric of the portion of the non-volatile memory components among a remainder of the non-volatile memory components; and
selecting the portion of the non-volatile memory components based on the ranking.
4. The system of claim 1 , wherein the identifying the portion of the non-volatile memory components based on the performance test further comprises:
performing the performance test upon the non-volatile memory components;
determining a performance metric of the non-volatile memory components based on the performance test; and
determining a ranking of the portion of the non-volatile memory components among the non-volatile memory components based on the performance.
5. The system of claim 1 , wherein the non-volatile memory components comprise a set of flash blocks, and the identifying the portion of the non-volatile memory components comprises:
determining a write time of each flash block among the set of flash blocks of the non-volatile memory components;
ranking the set of flash blocks based on the write time of each flash block among the set of flash blocks; and
identifying the portion of the non-volatile memory components based on the ranking of the set of flash blocks.
6. The system of claim 1 , wherein the non-volatile memory components comprise NAND flash memory that comprises single-level cell NAND flash memory.
7. The system of claim 1 , wherein the portion of the non-volatile memory components is a first portion, and the operations further comprise:
performing the performance test upon the non-volatile memory components at a predetermined interval;
determining a first performance metric of the first portion of the non-volatile memory components transgresses a minimum threshold value;
identifying a second portion of the non-volatile memory components based on a second performance metric of the second portion of the non-volatile memory components; and
moving the data to the second portion of the non-volatile memory components.
8. The system of claim 1 , wherein the non-volatile memory components include a single-level cell (SLC) flash memory.
9. A method comprising:
detecting, by at least one hardware processor, a power loss at a device associated with a plurality of memory components, the plurality of memory components comprising non-volatile memory components and a volatile cache;
identifying, by the at least one hardware processor, data written to the volatile cache;
administering, by the at least one hardware processor, a performance test upon the non-volatile memory components, the performance test including a latency test;
identifying, by the at least one hardware processor, a portion of the non-volatile memory components based on the performance test;
accessing, by the at least one hardware processor, the data written to the volatile cache responsive to the power loss; and
moving, by the at least one hardware processor, the data to the portion of the non-volatile memory components.
10. The method of claim 9 , wherein the identifying the portion of the non-volatile memory components based on the performance test further comprises:
performing the performance test upon the non-volatile memory components at a predefined interval; and
identifying the portion of the non-volatile memory components based on the performance test.
11. The method of claim 9 , wherein the identifying the portion of the non-volatile memory components based on the performance test further comprises:
determining a ranking of the portion of the non-volatile memory components based on a performance metric of the portion of the non-volatile memory components among a remainder of the non-volatile memory components; and
selecting the portion of the non-volatile memory components based on the ranking.
12. The method of claim 9 , wherein the identifying the portion of the non-volatile memory components further comprises:
performing the performance test upon the non-volatile memory components;
determining a performance metric of the non-volatile memory components based on the performance test; and
determining a ranking of the portion of the non-volatile memory components among the non-volatile memory components based on the performance.
13. The method of claim 9 , wherein the non-volatile memory components comprise a set of flash blocks, and the identifying the portion of the non-volatile memory components comprises:
determining a write time of each flash block among the set of flash blocks of the non-volatile memory components;
ranking the set of flash blocks based on the write time of each flash block among the set of flash blocks; and
identifying the portion of the non-volatile memory components based on the ranking of the set of flash blocks.
14. The method of claim 9 , wherein the non-volatile memory components comprise NAND flash memory that comprises single-level cell NAND flash memory.
15. The method of claim 9 , wherein the portion of the non-volatile memory components is a first portion, and the method further comprises:
performing the performance test upon the non-volatile memory components at a predetermined interval;
determining a first performance metric of the first portion of the non-volatile memory components transgresses a minimum threshold value;
identifying a second portion of the non-volatile memory components based on a second performance metric of the second portion of the non-volatile memory components; and
moving the data to the second portion of the non-volatile memory components.
16. The method of claim 9 , wherein the non-volatile memory components include a single-level cell (SLC) flash memory.
17. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:
detecting a power loss at a device associated with a plurality of memory components, the plurality of memory components comprising non-volatile memory components and a volatile cache;
identifying data written to the volatile cache;
administering a performance test upon the non-volatile memory components, the performance test including a latency test;
identifying a portion of the non-volatile memory components based on the performance test;
accessing the data written to the volatile cache responsive to the power loss; and
moving the data to the portion of the non-volatile memory components.
18. The non-transitory computer-readable storage medium of claim 17 , wherein the identifying the portion of the non-volatile memory components based on the performance test further comprises:
performing the performance test upon the non-volatile memory components at a predefined interval; and
identifying the portion of the non-volatile memory components based on the performance test.
19. The non-transitory computer-readable storage medium of claim 17 , wherein the identifying the portion of the non-volatile memory components based on the performance test further comprises:
determining a ranking of the portion of the non-volatile memory components based on a performance metric of the portion of the non-volatile memory components among a remainder of the non-volatile memory components; and
selecting the portion of the non-volatile memory components based on the ranking.
20. The non-transitory computer-readable storage medium of claim 17 , wherein the non-volatile memory components include a single-level cell (SLC) flash memory.