Serial attached non-volatile memory
Systems and methods for enabling serial attached Non-Volatile (NV) memory are provided. In some embodiments, a method of operation of a computing system including: in an NV Random Access Memory module (NVRAM) having a non-volatile device, a volatile memory device with data, a NV Controller unit (NVC), and a serial host interface, the method includes: receiving a request for data on the serial host interface and providing the requested data, from the volatile memory device with data, on the serial host interface. The method also includes: detecting a disruptive volatile memory event; copying the data of the volatile memory device to the NV device based on the disruptive volatile memory event; and restoring the data of the volatile memory device from the NV device. In this way, Dynamic Random-Access Memory (DRAM) level endurance and speed/latency can be provided while making it NV.
1. A method of operation of a computing system comprising: in a Non-Volatile Random Access Memory module (NVRAM) having a non-volatile device, a volatile memory device with data, a non-volatile controller unit, and a serial host interface, the method comprising:
receiving a request for data on the serial host interface;
providing the requested data, from the volatile memory device with data, on the serial host interface;
detecting a disruptive volatile memory event;
copying the data of the volatile memory device to the non-volatile device based on the disruptive volatile memory event; and
restoring the data to the volatile memory device from the non-volatile device;
where providing the requested data comprises providing the requested data with byte access on the serial host interface.
2. The method as claimed in claim 1 wherein the non-volatile device comprises one or more of the group consisting of: a NAND Flash device, a Phase Change Memory (PCM), Resistive Random Access Memory (RERAM), Magnetoresistive Random Access Memory (MRAM), and Nano Random Access Memory (NRAM).
3. The method as claimed in claim 1 wherein the volatile memory device with data comprises a Dynamic Random-Access Memory (DRAM) device.
4. The method as claimed in claim 1 wherein the serial host interface comprises a Peripheral Component Interconnect Express (PCIe) interface.
5. The method as claimed in claim 1 wherein the serial host interface comprises a Compute Express Link (CXL) interface.
6. The method as claimed in claim 1 wherein the serial host interface comprises one or more of the group consisting of: an OpenCAPI Memory Interface (OMI); a Cache Coherent Interconnect for Accelerators (CCIX) interface; and a Gen-Z interface.
7. The method as claimed in claim 1 wherein detecting the disruptive volatile memory event comprises detecting a power loss event.
8. The method as claimed in claim 7 wherein the power loss event is scheduled.
9. The method as claimed in claim 7 wherein the power loss event is unscheduled.
10. The method as claimed in claim 1 further comprising:
in response to detecting the disruptive volatile memory event, providing power to the volatile memory device while copying the data of the volatile memory device to the non-volatile device.
11. A computing system comprising: a Non-Volatile Random Access Memory module (NVRAM) having a non-volatile device, a volatile memory device with data, a non-volatile controller unit, and a serial host interface;
the non-volatile controller unit configured to:
receive a request for data on the serial host interface;
provide the requested data, from the volatile memory device with data, on the serial host interface;
detect a disruptive volatile memory event;
copy the data of the volatile memory device to the non-volatile device based on the disruptive volatile memory event; and
restore the data of the volatile memory device from the non-volatile device;
where providing the requested data comprises providing the requested data with byte access on the serial host interface.
12. The computing system as claimed in claim 11 wherein the non-volatile device comprises one or more of the group consisting of: a NAND Flash device, a Phase Change Memory (PCM), Resistive Random Access Memory (RERAM), Magnetoresistive Random Access Memory (MRAM), and Nano Random Access Memory (NRAM).
13. The computing system as claimed in claim 11 wherein the volatile memory device with data comprises a Dynamic Random-Access Memory (DRAM) device.
14. The computing system as claimed in claim 11 wherein the serial host interface comprises a Peripheral Component Interconnect Express (PCIe) interface.
15. The computing system as claimed in claim 11 wherein the serial host interface comprises a Compute Express Link (CXL) interface.
16. The computing system as claimed in claim 11 wherein the serial host interface comprises one or more of the group consisting of: an OpenCAPI Memory Interface (OMI); a Cache Coherent Interconnect for Accelerators (CCIX) interface; and a Gen-Z interface.
17. The computing system as claimed in claim 11 wherein detecting the disruptive volatile memory event comprises detecting a power loss event.
18. The computing system as claimed in claim 17 wherein the power loss event is scheduled.
19. The computing system as claimed in claim 17 wherein the power loss event is unscheduled.
20. The computing system as claimed in claim 11 wherein the non-volatile controller unit is further configured to:
in response to detecting the disruptive volatile memory event, provide power to the volatile memory device while copying the data of the volatile memory device to the non-volatile device.