Double program debug method for NAND memory using self-verification by internal firmware
The present disclosure provides a method for debugging of flash memory devices using NAND self-verification The method can include programming a selected page of the NAND flash memory device according to first and second programming data. The selected page can include a plurality of memory cells corresponding to a word line. The programming of the selected page can include a plurality of programming operations and a plurality of verifying operations. Ones of the plurality of verifying operations can be performed after corresponding ones of the plurality of programming operations to determine whether programmed memory cells of the selected page have threshold voltage levels according to the first or second programming data. The method can also include performing self-verification on the selected page to determine whether data stored at the selected page was overwritten and generating a fail indication upon determining that the data stored at the selected page was overwritten.
1. A programming method for a NAND flash memory device, comprising:
programming a selected page of the NAND flash memory device according to first and second programming data, wherein the selected page comprises a plurality of memory cells corresponding to a word line, and wherein the programming of the selected page comprises:
a plurality of programming operations using a plurality of programming voltages; and
a plurality of verifying operations, wherein ones of the plurality of verifying operations are performed after corresponding ones of the plurality of programming operations to determine whether programmed memory cells of the selected page have threshold voltage levels according to the first or second programming data;
performing a self-verification on the selected page, by the NAND flash memory device, to determine whether data stored at the selected page was overwritten; and
generating a fail indication upon determining that the data stored at the selected page was overwritten.
2. The programming method of claim 1 , wherein:
the programming of the selected page is associated with a memory controller-implemented program of the NAND flash memory device; and
the programming method further comprises:
stopping the memory controller-implemented program in response to the generating of the fail indication, and
debugging the memory controller-implemented program based on a timing of the stopping of the memory controller-implemented program.
3. The programming method of claim 1 , wherein the self-verification comprises performing an internal read operation on the selected page by the NAND flash memory device to determine the data stored at the selected page.
4. The programming method of claim 3 , further comprising comparing data determined from the internal read operation on the selected page and the first or second programming data, wherein
the generating of the fail indication comprises determining, based on the comparing, a fail result if a failed-bit count is above a threshold.
5. The programming method of claim 1 , further comprising receiving, by the NAND memory, an input to adjust the performing of the self-verification.
6. The programming method of claim 5 , further comprising limiting the performing of the self-verification to one or more regions of the NAND flash memory device specified by the input, wherein the one or more specified regions comprises at least one of;
a region used for single-level cells (SLC);
a region used for multi-level cells (MLC);
a region used for triple-level cells (TLC);
a region used for quad-level cells (QLC);
a page;
a block; and
a plane.
7. The programming method of claim 1 , further comprising delaying a caching of future programming data until after the performing of the self-verification.
8. A NAND flash memory device comprising:
a memory array comprising a plurality of pages, each page of the plurality of pages comprising a plurality of memory cells corresponding to a word line; and
a peripheral circuit coupled to the plurality of pages via the word line and configured to program a selected page of the NAND flash memory device according to first and second programming data using:
a plurality of programming operations using a plurality of programming voltages;
a plurality of verifying operations, wherein ones of the plurality of verifying operations are performed after corresponding ones of the plurality of programming operations to determine whether programmed memory cells of the selected page have threshold voltage levels according to the first or second programming data; and
a self-verification operation on the selected page to determine whether data stored at the selected page was overwritten,
wherein the NAND flash memory device is configured to generate a fail indication upon determining that the data stored at the selected page was overwritten.
9. The NAND flash memory device of claim 8 , wherein:
the programming of the selected page is associated with a memory controller-implemented program of the NAND flash memory device;
the peripheral circuit is further configured to stop the memory controller-implemented program in response to the generating of the fail indication; and
the NAND flash memory device is further configured to communicate with a host-implemented program to debug the memory controller-implemented program based on a timing of the stopping of the memory controller-implemented program.
10. The NAND flash memory device of claim 8 , wherein the self-verification comprises performing an internal read operation on the selected page by the NAND flash memory device to determine the data stored at the selected page.
11. The NAND flash memory device of claim 10 , wherein:
the NAND flash memory device is further configured to compare data determined from the internal read operation on the selected page and the first or second programming data; and
the generating of the fail indication comprises determining, based on the comparing, a fail result if a failed-bit count is above a threshold.
12. The NAND flash memory device of claim 8 , wherein the NAND flash memory device is further configured to receive an input to adjust the performing of the self-verification.
13. The NAND flash memory device of claim 12 , wherein the NAND flash memory device is further configured to limit the performing of the self-verification to one or more regions of the NAND flash memory device specified by the input, wherein the one or more specified regions comprises at least one of:
a region used for single-level cells (SLC);
a region used for multi-level cells (MLC);
a region used for triple-level cells (TLC);
a region used for quad-level cells (QLC);
a page;
a block; and
a plane.
14. The NAND flash memory device of claim 8 , wherein the NAND flash memory device is configured to delay a caching of future programming data until after the performing of the self-verification.
15. A system comprising:
one or more computing devices; and
a NAND flash memory device comprising:
a memory array comprising a plurality of pages, each page of the plurality of pages comprising a plurality of memory cells corresponding to a word line; and
a peripheral circuit coupled to the plurality of pages via the word line and configured to:
program a selected page of the NAND flash memory device according to first and second programming data, wherein the programming of the selected page comprises:
a plurality of programming operations using a plurality of programming voltages; and
a plurality of verifying operations, wherein ones of the plurality of verifying operations are performed after corresponding ones of the plurality of programming operations to determine whether programmed memory cells of the selected page have threshold voltage levels according to the first or second programming data; and
perform a self-verification on the selected page to determine whether data stored at the selected page was overwritten; and
wherein the NAND flash memory device is configured to generate a fail indication upon determining that data stored at the selected page was overwritten.
16. The system of claim 15 , wherein:
the programming of the selected page is associated with a memory controller-implemented program of the NAND flash memory device;
the peripheral circuit is further configured to stop the memory controller-implemented program in response to the generating of the fail indication; and
the one or more computing devices are configured to debug the memory controller-implemented program based on a timing of the stopping of the memory controller-implemented program.
17. The system of claim 15 , wherein the self-verification comprises performing an internal read operation on the selected page by the NAND flash memory device to determine the data stored at the selected page.
18. The system of claim 17 , wherein:
the NAND flash memory device is further configured to compare data determined from the internal read operation on the selected page and the first or second programming data; and
the generating of the fail indication comprises determining, based on the comparing, a fail result if the failed-bit count is above a threshold.
19. The system of claim 17 , wherein the NAND flash memory device is configured to receive an input to adjust the performing of the internal read operation.
20. The system of claim 19 , wherein the NAND flash memory device is further configured to limit the performing of the self-verification to one or more regions of the NAND flash memory device specified by the input, wherein the one or more specified regions comprises at least one of:
a region used for single-level cells (SLC);
a region used for multi-level cells (MLC);
a region used for triple-level cells (TLC);
a region used for quad-level cells (QLC);
a page;
a block; and
a plane.