Granted Patent B2

US 12,475,049 · App. 17/705,015 · Granted Nov 18, 2025

Inventors: Leon Polishuk (Haifa, IL); Oz Shitrit (Tel Aviv, IL); Elyada Bar-Chaim (Haifa, IL); Mauricio Valverde Monge (Hillsboro, OR); Ayan Mandal (Bangaluru, IN)

Assignee: Intel Corporation

G06F12/0815G06F12/0811G06F12/0833G06F12/0864

Abstract

Claims (70)

1 . A device comprising:

one or more ports to couple the device to one or more processors comprising a first cache;

a first array of memory cells, wherein the first array comprises a first plurality of sets each comprising respective ways; and

first circuitry coupled to the one or more ports and to the first array, the first circuitry to provide a snoop filter with the first array, comprising the first circuitry to enable each set of the first plurality of sets to be available as a candidate to store coherency information regarding first data which is to be stored by a respective first set of the first cache;

wherein:

the first cache further comprises a respective second set;

the first array further comprises a second plurality of sets; and

the first circuitry to provide the snoop filter with the first array further comprises the first circuitry to enable each set of the second plurality of sets to be available as a candidate to store coherency information regarding second data which is to be stored by the respective second set of the first cache.

2 . The device of claim 1 , wherein multiple caches of the one or more processors comprise the first cache;

wherein the multiple caches each comprise a respective first set; and

wherein, for each set of the first plurality of sets, any line in the first cache which is to be represented by the set is to be a line in the respective first sets of the multiple caches.

3 . The device of claim 2 , wherein the multiple caches each comprise a respective second set; and

wherein, for each set of the second plurality of sets, any line of a cache which is to be represented by the set is to be a line in the respective second sets of the multiple caches.

4 . The device of claim 1 , wherein the first circuitry is further to:

detect a data access request from the one or more processors;

based on the data access request, perform a selection of the first plurality of sets from among multiple sets of the snoop filter; and

based on the selection, search the first plurality of sets for an entry which corresponds to the data access request.

5 . The device of claim 4 , wherein multiple tags each correspond to a different respective set of the first plurality of sets;

wherein a first tag of the multiple tags comprises a first bit sequence;

wherein the first circuitry is to perform the selection based on a second bit sequence which is equal to a result of a removal of one or more bits from the first bit sequence.

6 . The device of claim 5 , wherein the second bit sequence is equal to a result of a removal of a least significant bit from the first bit sequence.

7 . The device of claim 1 , the first circuitry further to identify a location, in multiple caches, which is to receive data, comprising the first circuitry to:

select a first way from among all of multiple ways of the multiple caches, wherein the multiple ways each meet one or more criteria;

select a second way from among only those of the multiple ways which are each represented by a first set of the snoop filter;

where it is determined that only a cache victim is needed, select the first way over the second way to be a victim; and

where it is determined that both a cache victim and a snoop filter victim is needed, select the second way over the first way to be the victim.

8 . A method comprising:

providing a snoop filter with a first array of memory cells, wherein the first array comprises a first plurality of sets each comprising respective ways, wherein providing the snoop filter comprises enabling each set of the first plurality of sets to be available as a candidate to store coherency information regarding first data which is to be stored by a respective first set of a first cache;

detecting a data access request from one or more processors;

based on the data access request, performing a selection of the first plurality of sets from among multiple sets of the snoop filter; and

based on the selection, searching the first plurality of sets for an entry which corresponds to the data access request;

wherein:

the first cache further comprises a respective second set;

the first array further comprises a second plurality of sets; and

providing the snoop filter with the first array further comprises enabling each set of the second plurality of sets to be available as a candidate to store coherency information regarding second data which is to be stored by the respective second set of the first cache.

9 . The method of claim 8 , wherein multiple caches of the one or more processors comprise the first cache;

wherein the multiple caches each comprise a respective first set; and

wherein, for each set of the first plurality of sets, any line in the first cache which is represented by the set is a line in the respective first sets of the multiple caches.

10 . The method of claim 8 , wherein multiple tags each correspond to a different respective set of the first plurality of sets;

wherein a first tag of the multiple tags comprises a first bit sequence;

wherein the selection is performed based on a second bit sequence which is equal to a result of a removal of one or more bits from the first bit sequence.

11 . The method of claim 8 , further comprising identifying a location, in multiple caches, which is to receive data, wherein identifying the location comprises:

selecting a first way from among all of multiple ways of the multiple caches, wherein the multiple ways each meet one or more criteria;

selecting a second way from among only those of the multiple ways which are each represented by a first set of the snoop filter;

where it is determined that only a cache victim is needed, selecting the first way over the second way to be a victim; and

where it is determined that both a cache victim and a snoop filter victim is needed, selecting the second way over the first way to be the victim.

12 . A system comprising:

one or more processors comprising a first cache;

an integrated circuit (IC) coupled to the one or more processors via one or more ports, the IC comprising:

a first array of memory cells, wherein the first array comprises a first plurality of sets each comprising respective ways; and

first circuitry coupled to the one or more ports and to the first array, the first circuitry to provide a snoop filter with the first array, comprising the first circuitry to enable each set of the first plurality of sets to be available as a candidate to store coherency information regarding first data which is to be stored by a respective first set of the first cache;

wherein the first circuitry is further to identify a location, in multiple caches, which is to receive data, comprising the first circuitry to:

select a first way from among all of multiple ways of the multiple caches, wherein the multiple ways each meet one or more criteria;

select a second way from among only those of the multiple ways which are each represented by a first set of the snoop filter;

where it is determined that only a cache victim is needed, select the first way over the second way to be a victim; and

where it is determined that both a cache victim and a snoop filter victim is needed, select the second way over the first way to be the victim; and

a display device coupled to the one or more processors, the display device to display an image based on the first data.

13 . The system of claim 12 , wherein multiple caches of the one or more processors comprise the first cache;

wherein the multiple caches each comprise a respective first set; and

wherein, for each set of the first plurality of sets, any line in the first cache which is to be represented by the set is to be a line in the respective first sets of the multiple caches.

14 . The system of claim 13 , wherein the first cache further comprises a respective second set;

wherein the first array further comprises a second plurality of sets; and

wherein the first circuitry to provide the snoop filter with the first array further comprises the first circuitry to enable each set of the second plurality of sets to be available as a candidate to store coherency information regarding second data which is to be stored by the respective second set of the first cache.

15 . The system of claim 12 , wherein the first cache further comprises a respective second set;

wherein the first array further comprises a second plurality of sets; and

wherein the first circuitry to provide the snoop filter with the first array further comprises the first circuitry to enable each set of the second plurality of sets to be available as a candidate to store coherency information regarding second data which is to be stored by the respective second set of the first cache.

16 . The system of claim 12 , wherein the first circuitry is further to:

detect a data access request from the one or more processors;

based on the data access request, perform a selection of the first plurality of sets from among multiple sets of the snoop filter; and

based on the selection, search the first plurality of sets for an entry which corresponds to the data access request.

Assignments (1)

Continuity (1)

References Cited (14)