Embedded component and methods of making the same
Various embodiments disclosed relate to a substrate for a semiconductor device. The substrate includes a first major surface and a second major surface opposite the first major surface. The substrate further includes a cavity defined by a portion of the first major surface. The cavity includes a bottom dielectric surface and a plurality of sidewalls extending from the bottom surface to the first major surface. A first portion of a first sidewall includes a conductive material.
1. A method of forming a semiconductor package comprising:
forming a cavity in a substrate having a height defined between a first major surface and an opposed second major surface to expose at least a portion of a plurality of vias extending along a sidewall of the cavity; and
positioning an electrical component in the cavity, wherein the electrical component contacts the plurality of vias.
2. The method of claim 1 , wherein the cavity is formed by cutting the substrate.
3. The method of claim 1 , further comprising soldering a connection between the electrical component and the exposed portion of at least one of the vias.
4. The method of claim 1 , wherein forming the cavity comprises cutting through the portion of the plurality of vias.
5. The method of claim 1 , wherein the electrical component comprises a silicon die.
6. The method of claim 5 , wherein the silicon die is at least one of a central processing unit, a flash memory, a wireless charger, a power management integrated circuit (PMIC), a Wi-Fi transmitter, and a global positioning system, and a NAND stack.
7. The method of claim 1 , wherein forming the cavity comprises cutting through the portion of the plurality of vias.
8. The method of claim 7 , wherein the plurality of vias are cut in half in a z-direction.
9. The method of claim 1 , wherein the electrical component is at least one of a capacitor, a resistor, and an inductor.
10. The method of claim 1 , wherein the cavity is cut to a depth ranging from about 10 height % to about 90 height % of the substrate.
11. The method of claim 1 , wherein the cavity comprises:
an exposed bottom dielectric surface that is substantially free of any conductive material;
a plurality of sidewalls extending from the bottom surface to the first major surface, wherein the plurality of sidewalls comprises a conductive material along an entire height of the plurality of sidewalls.
12. The method of claim 1 , wherein the electrical component is disposed in the cavity and in electrical contact with a plurality of sidewalls along an entire height of the plurality of sidewalls.