Integrated functional and design for testability (DFT) clock delivery architecture
An aspect of the disclosure relates to an integrated circuit (IC). The IC includes a first set of test clock controllers (TCCs) including a first set of clock outputs, respectively; and a first set of functional cores including a first set of clock inputs coupled to the first set of clock outputs of the first set of TCCs, respectively.
1. An integrated circuit (IC), comprising:
a first set of test clock controllers (TCCs) including a first set of clock outputs, respectively, wherein the first set of TCCs comprises:
a first set of clock inputs configured to receive a set of at-speed clocks, respectively,
a second set of clock inputs configured to receive a first shift test clock, and
a first set of functional/test interfaces configured to receive control signals indicating a mode of operation, respectively; and
a first set of functional cores including a first set of clock inputs coupled to the first set of clock outputs of the first set of TCCs, respectively.
2. The IC of claim 1 , wherein the first set of TCCs are configured to select the set of at-speed clocks or the first shift test clock to generate a set of output clocks at the first set of clock outputs based on the control signals received via the first set of functional/test interfaces, respectively.
3. The IC of claim 2 , wherein the first set of TCCs are configured to select the set of at-speed clocks to generate the set of output clocks in response to the control signals indicating a functional mode of operation, respectively.
4. The IC of claim 2 , wherein the first set of TCCs are configured to select the set of at-speed clocks to generate the set of output clocks in response to the control signals indicating a capture test mode of operation, respectively.
5. The IC of claim 2 , wherein the first set of TCCs are configured to select the first shift test clock to generate the set of output clocks in response to the control signals indicating a shift test mode of operation, respectively.
6. The IC of claim 1 , wherein the first set of TCCs further comprises a third set of clock inputs configured to receive a second shift test clock.
7. The IC of claim 1 , further comprising a set of clock generators, comprising:
a set of multiplexers, comprising:
a third set of clock inputs configured to receive a first at-speed base clock, respectively;
a fourth set of clock inputs configured to receive a second at-speed base clock, respectively;
a set of select inputs, respectively; and
a second set of clock outputs, respectively;
a set of clock frequency dividers comprising:
a fifth set of clock inputs coupled to the second set of clock outputs of the set of multiplexers, respectively; and
a third set of clock outputs coupled to the first set of clock inputs of the first set of TCCs, respectively; and
a second set of functional/test interfaces coupled to the set of select inputs of the set of multiplexers, respectively.
8. The IC of claim 7 , wherein the set of clock generators are configured to select the first at-speed base clock to generate the set of at-speed clocks in response to a first set of control signals received via the second set of functional/test interfaces indicating a first mode of operation, respectively.
9. The IC of claim 8 , wherein the set of clock generators are configured to select the second at-speed base clock to generate the set of at-speed clocks in response to a second set of control signals received via the second set of functional/test interfaces indicating a second mode of operation, respectively.
10. The IC of claim 7 , wherein:
a first subset of one or more of the set of clock generators are configured to select the first at-speed base clock to generate a first subset of the set of at-speed clocks in response to a first set of control signals received via a first subset of the second set of functional/test interfaces, respectively; and
a second subset of one or more of the set of clock generators are configured to select the second at-speed base clock to generate a second subset of the set of at-speed clocks in response to a second set of control signals received via a second subset of the second set of functional/test interfaces, respectively.
11. The IC of claim 7 , wherein the set of clock generators are configured to frequency divide the first at-speed base clock or the second at-speed base clock to generate the set of at-speed clocks in response to control signals received via the second set of functional/test interfaces, respectively.
12. The IC of claim 7 , further comprising at least one clock frequency divider comprising:
at least one clock input coupled to at least one of the second set of clock outputs of at least one of the set of clock generators, respectively;
at least one clock output coupled to at least one of the first set of clock inputs of the first set of TCCs; and
at least one functional/test interface.
13. The IC of claim 12 , wherein the at least one clock frequency divider is configured to frequency divide at least one of the set of at-speed clocks to generate at least another of the set of at-speed clocks based on control signals indicating at least one divider ratio received via the at least one functional/test interface, respectively.
14. The IC of claim 7 , further comprising:
a first phase locked loop (PLL) comprising:
a first clock input configured to receive a reference clock;
a first functional/test interface; and
a first clock output configured to generate the first at-speed base clock based on a first control signal received via the first functional/test interface; and
a second PLL comprising:
a second clock input configured to receive the reference clock;
a second functional/test interface; and
a second clock output configured to generate the second at-speed base clock based on a second control signal received via the second functional/test interface.
15. The IC of claim 14 , wherein the first control signal specifies a first divider ratio for a first programmable divider situated in a first feedback path of the first PLL, and wherein the second control signal specifies a second divider ratio for a second programmable divider situated in a second feedback path of the second PLL.
16. The IC of claim 1 , further comprising:
a second set of test clock controllers (TCCs) comprising:
a second set of clock inputs coupled to the first set of clock outputs of the first set of TCCs, respectively; and
a second set of clock outputs; and
a second set of functional cores including a second set of clock inputs coupled to the second set of clock outputs of the second set of TCCs, respectively.
17. The IC of claim 16 , wherein:
the first set of TCCs comprises:
a third set of clock inputs configured to receive a set of at-speed clocks, respectively; and
a fourth set of clock inputs configured to receive a shift test clock, respectively; and
a first set of functional/test interfaces, respectively; and
the second set of TCCs further comprises:
a fifth set of clock inputs configured to receive the first shift test clock, respectively;
a second set of functional/test interfaces, respectively.
18. The IC of claim 1 , wherein the first set of functional cores comprises:
a set of scan chains, respectively;
a set of functional circuits coupled to the set of scan chains, respectively; and
a set of functional/test interfaces, respectively.
19. The IC of claim 18 , wherein the set of scan chains are configured to shift-in and shift-out test vectors under sequential control of a first set of clocks received from the first set of clock outputs of the first set of TCCs in response to control signals indicating a shift test mode of operation received via the set of functional/test interfaces, respectively.
20. The IC of claim 19 , wherein the set of scan chains are configured to provide and receive functional or test data from the set of functional circuits under sequential control of a second set of clocks received from the first set of clock outputs of the first set of TCCs in response to control signals indicating a functional or capture test mode of operation received via the set of functional/test interfaces, respectively.
21. A method, comprising:
receiving, by a set of test clock controllers (TCCs) via a set of functional/test interfaces, control signals indicating a mode of operation, respectively;
providing, by the set of TCCs, a set of at-speed clocks to a set of functional cores in response to the mode of operation being a first test mode of operation, respectively; and
providing, by the set of TCCs, the set of at-speed clocks to the set of functional cores in response to the mode of operation being a functional mode of operation, respectively.
22. The method of claim 21 , wherein the first test mode of operation comprises a capture test mode of operation.
23. The method of claim 21 , further comprising providing a shift test clock to the set of functional cores in response to the mode of operation being a second test mode of operation.
24. The method of claim 23 , wherein the second test mode of operation comprises a shift test mode of operation.
25. An apparatus, comprising:
means for receiving, via a set of functional/test interfaces, control signals indicating a mode of operation, respectively;
means for providing a set of at-speed clocks to a set of functional cores in response to the mode of operation being a first test mode of operation, respectively; and
means for providing the set of at-speed clocks to the set of functional cores in response to the mode of operation being a functional mode of operation, respectively.
26. The apparatus of claim 25 , wherein the first test mode of operation comprises a capture test mode of operation.
27. The apparatus of claim 25 , further comprising means for providing a shift test clock to the set of functional cores in response to the mode of operation being a second test mode of operation.
28. The apparatus of claim 27 , wherein the second test mode of operation comprises a shift test mode of operation.
29. A wireless communication device, comprising:
at least one antenna;
a transceiver coupled to the at least one antenna;
a set of digital signal processing cores coupled to the transceiver; and
a clock delivery system, comprising a first set of test clock controllers (TCCs) including a set of clock outputs coupled to a set of clock inputs of the set of digital signal processing cores, respectively, wherein the first set of TCCs further includes:
a first set of clock inputs configured to receive a set of at-speed clocks, respectively,
a second set of clock inputs configured to receive a first shift test clock, and
a first set of functional/test interfaces configured to receive control signals indicating a mode of operation, respectively.