Methods of manufacturing a semiconductor device with local isolation and a semiconductor device with local isolation
View Patent ↗In a method of manufacturing a semiconductor device a fin structure is formed in which first semiconductor layers and second semiconductor layers are alternately stacked over a substrate. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure that is not covered by the sacrificial gate structure is etched to form a source/drain space. An isolation region is formed at a bottom portion of the source/drain space. A source/drain epitaxial layer is formed over the isolation region in the source/drain space, and a void region in the isolation region is produced between the source/drain epitaxial layer and the substrate to cause electrical isolation between the source/drain region and the substrate.
1 . A method of manufacturing a semiconductor device, comprising:
forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked over a substrate;
forming a sacrificial gate structure over the fin structure;
etching a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a source/drain space;
forming an isolation region at a bottom portion of the source/drain space;
forming a source/drain epitaxial layer over the isolation region in the source/drain space; and
producing a void region in the isolation region between the source/drain epitaxial layer and the substrate, wherein the void region has a bottom surface coplanar with a bottom surface of a lowest second semiconductor layer, and the bottom surface of the void region is aligned with a top surface of a lowest first semiconductor layer.
2 . The method of claim 1 , wherein forming the isolation region further comprises forming a dielectric region in the isolation region, wherein the void region is produced between the source/drain epitaxial layer and the dielectric region.
3 . The method of claim 1 , wherein forming the isolation region further comprises forming an insulating layer in the isolation region, wherein the void region is produced between the source/drain epitaxial layer and the insulating layer.
4 . The method of claim 1 , further comprising:
disposing a dielectric layer at a bottom of the source/drain space, wherein the source/drain epitaxial layer is formed over the dielectric layer and the void region is produced between the dielectric layer and the source/drain epitaxial layer.
5 . The method of claim 4 , wherein the isolation region comprises the dielectric layer and the void region.
6 . The method of claim 1 , wherein forming the isolation region further comprises forming an insulating layer over an undoped epitaxial layer in the isolation region, wherein the void region is between the source/drain epitaxial layer and the insulating layer.
7 . The method of claim 1 , wherein forming the isolation region further comprises:
forming an undoped epitaxial layer in the isolation region; and
ion implanting the undoped epitaxial layer with a gas, wherein the void region is produced between the source/drain epitaxial layer and the undoped epitaxial layer.
8 . The method of claim 7 , wherein the gas is either nitrogen or an inert gas.
9 . A method of manufacturing a semiconductor device, comprising:
forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked;
forming a sacrificial gate structure over the fin structure;
etching a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a source/drain space;
forming cavities on an end of each of the first semiconductor layers where the first semiconductor layers intersect with the source/drain space by laterally etching the first semiconductor layers through the source/drain space;
forming an inner spacer made of a dielectric material in the cavities of the first semiconductor layers;
forming an electrical isolation region at a bottom of the source/drain region, wherein the electrical isolation region produces an electrical barrier, the electrical isolation region includes a void region, and an interface between a lowest first semiconductor layer and a lowest second semiconductor layer is aligned with a bottom surface of the void region; and
forming a doped source/drain epitaxial layer over the electrical isolation region in the source/drain space.
10 . The method of claim 9 , wherein at least one process selected from the group consisting of a lithography process and an etching process is performed after the electrical isolation region is formed and before the doped source/drain epitaxial layer is formed.
11 . The method of claim 9 , wherein the electrical isolation region is formed by:
epitaxially disposing an undoped layer; and
ion implanting the undoped layer with a dopant of opposite type of a dopant of the doped source/drain epitaxial layer.
12 . The method of claim 9 , wherein forming the electrical isolation region further comprises forming a dielectric region in the electrical isolation region, wherein the void region is produced between the doped source/drain epitaxial layer and the dielectric region.
13 . The method of claim 9 , wherein forming the electrical isolation region further comprises forming an insulating layer in the electrical isolation region, wherein the void region is produced between the doped source/drain epitaxial layer and the insulating layer.
14 . The method of claim 9 , wherein the electrical barrier is either a voltage barrier or a current barrier.
15 . A method of manufacturing a semiconductor device, comprising:
forming a fin structure over a substrate, wherein the fin structure includes channel semiconductor layers and sacrificial semiconductor layers alternately stacked;
forming a sacrificial gate structure over the fin structure;
etching a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a source/drain space;
forming an isolation region at a bottom portion of the source/drain space; and
forming a source/drain epitaxial layer over the isolation region in the source/drain space, wherein the isolation region includes a dielectric region, an insulating layer in the isolation region, and a void region between the source/drain epitaxial layer and the insulating layer and between the source/drain epitaxial layer and the dielectric region.
16 . The method of claim 15 , wherein forming the isolation region further comprises forming an insulating layer over an undoped epitaxial layer in the isolation region, wherein the void region is between the source/drain epitaxial layer and the insulating layer.
17 . The method of claim 15 , wherein the dielectric region has a top surface coplanar with a top surface of the insulating layer.
18 . The method of claim 15 , wherein the insulating layer has a top surface coplanar with an interface between a lowest first semiconductor layer and a lowest second semiconductor layer.
19 . The method of claim 15 , wherein the insulating layer includes a recess and the dielectric region is formed in the recess.
20 . The method of claim 15 , wherein the insulating layer includes a protrusion portion extending into a lowest first semiconductor layer.