Dynamic multilevel memory system
A system can dynamically migrate memory pages from near memory to far memory during runtime. A system basic input output system (BIOS) can program a first memory address space of size P and a second memory address space of size P to a near memory (NM) space of size (N) and a far memory (FM) space of size (M), where P equals N+M. For the first memory address space, the OS can manage the NM space and the FM space as a flat memory space with an address space of size P available. For the second memory address space, the OS can manage the NM space as a NM cache for FM, with an address space of size M available.
1. An apparatus comprising:
a processor to execute an operating system (OS), the OS to manage a near memory (NM) space of size (N) and a far memory (FM) space of size (M); and
a basic input output system (BIOS) to program a first memory address space of size P, where P equals N+M, to the NM space and the FM space, and to a program a second memory address space of size P to the NM space and the FM space;
wherein for the first memory address space, the OS is to manage the NM space and the FM space as a flat memory space in a one-level memory (1LM) configuration with an address space of size P available, and wherein for the second memory address space, the OS is to manage the NM space as a NM cache for FM in a two-level memory (2LM) configuration, with an address space of size M available, wherein the OS is to dynamically change between the 1LM configuration and the 2LM configuration at runtime; and
wherein the BIOS is to program a target address decoder (TAD) with a first region of size N for the NM, and a second region of size P, the second region having an address offset equal to P.
2. The apparatus of claim 1 , wherein the BIOS is to program a source address decoder (SAD) with a first region of size N for the NM, a second region of size M for the FM, and a third region of size P for a combination of the NM and the FM.
3. The apparatus of claim 1 , wherein the OS is to map a first memory page to the first memory address space, and to map a second memory page to the second memory address space.
4. The apparatus of claim 3 , wherein the OS is to migrate the first memory page at system runtime from the first memory address space to the second memory address space.
5. The apparatus of claim 4 , wherein to migrate the first memory page to the second memory address space, the OS is to:
vacate a first address region of the first memory address space that maps to the first memory page;
allocate a second address region of the second memory address space; and
map the first memory page to the second address region.
6. The apparatus of claim 3 , wherein the OS is to migrate the second memory page at system runtime from the second memory address space to the first memory address space.
7. The apparatus of claim 1 , wherein the near memory comprises double data rate (DDR) volatile memory.
8. The apparatus of claim 1 , wherein the far memory comprises a memory device compatible with a compute express link standard.
9. A system comprising:
a near memory device (NM) of size (N);
a far memory device (FM) of size (M);
a basic input output system (BIOS) to program a first memory address space of size P, where P equals N+M, including NM space for the NM and FM space for the FM, and to a program a second memory address space of size P including the NM space and the FM space; and
a processor to execute an operating system (OS), wherein for the first memory address space, the OS is to manage the NM space and the FM space as a flat memory space in a one-level memory (1LM) configuration with an address space of size P available, and wherein for the second memory address space, the OS is to manage the NM space as a NM cache for FM in a two-level memory (2LM) configuration, with an address space of size M available, wherein the OS is to dynamically change between the 1LM configuration and the 2LM configuration at runtime;
wherein the BIOS is to program a target address decoder (TAD) with a first region of size N for the NM, and a second region of size P, the second region having an address offset equal to P.
10. The system of claim 9 , wherein the BIOS is to program a source address decoder (SAD) with a first region of size N for the NM, a second region of size M for the FM, and a third region of size P for a combination of the NM and the FM.
11. The system of claim 9 , wherein the OS is to map a first memory page to the first memory address space, and to map a second memory page to the second memory address space, wherein the OS is to migrate the first memory page at system runtime from the first memory address space to the second memory address space.
12. The system of claim 11 , wherein to migrate the first memory page to the second memory address space, the OS is to:
vacate a first address region of the first memory address space that maps to the first memory page;
allocate a second address region of the second memory address space; and
map the first memory page to the second address region.
13. The system of claim 9 , wherein the OS is to map a first memory page to the first memory address space, and to map a second memory page to the second memory address space, wherein the OS is to migrate the second memory page at system runtime from the second memory address space to the first memory address space.
14. The system of claim 9 , including one or more of:
a host processor coupled to a memory controller;
a display communicatively coupled to a host processor;
a network interface communicatively coupled to a host processor; or
a battery to power the system.
15. A method for memory management, comprising:
programming a first memory address space of size P, where P equals N+M, to a near memory (NM) space of size (N) and a far memory (FM) space of size (M);
programming a second memory address space of size P to the NM space and the FM space;
programming a target address decoder (TAD) with a first region of size N for the NM, and a second region of size P, the second region having an address offset equal to P;
for the first memory address space, managing the NM space and the FM space as a flat memory space in a one-level memory (1LM) configuration with an address space of size P available;
for the second memory address space, managing the NM space as a NM cache for FM in a two-level memory (2LM) configuration, with an address space of size M available; and
dynamically changing between the 1LM configuration and the 2LM configuration at runtime.
16. The method of claim 15 , further comprising:
programming a source address decoder (SAD) with a first region of size N for the NM, a second region of size M for the FM, and a third region of size P for a combination of the NM and the FM.
17. The method of claim 15 , further comprising:
migrating a first memory page at system runtime from the first memory address space to the second memory address space.
18. The method of claim 15 , further comprising:
migrating a first memory page at system runtime from the second memory address space to the first memory address space.