Methods for performing multiple memory operations in response to a single command and memory devices and systems employing the same
View Patent ↗Memory devices, memory systems, and methods of operating memory devices and systems are disclosed in which a single command can trigger a memory device to perform multiple operations, such as a single refresh command that triggers the memory device to both perform a refresh command and to perform a mode register read. One such memory device comprises a memory, a mode register, and circuitry configured, in response to receiving a command to perform a refresh operation at the memory, to perform the refresh operation at the memory, and to perform a read of the mode register. The memory can be a first memory portion, the memory device can comprise a second memory portion, and the circuitry can be further configured, in response to the command, to provide on-die termination at the second memory portion of the memory system during at least a portion of the read of the mode register.
1. A memory device, comprising:
a memory; and
circuitry configured, in response to receiving a command to perform a first operation at the memory, to:
perform the first operation at the memory, and
perform a second operation of a different kind than the first operation, the second operation comprising a mode register read operation.
2. The memory device of claim 1 , wherein the first operation is a refresh operation.
3. The memory device of claim 1 , wherein the command includes a flag bit indicating that the mode register read operation is to be performed.
4. The memory device of claim 1 , wherein the mode register read operation includes outputting from the memory device data from a mode register of the memory device.
5. The memory device of claim 4 , wherein the outputted data includes information corresponding to a temperature of the memory.
6. The memory device of claim 5 , wherein the outputted data includes information corresponding to a refresh rate of the memory.
7. The memory device of claim 1 , wherein the command has a duration on a command/address bus of the memory device of a single clock cycle of the memory device.
8. A memory system, comprising:
a first memory portion;
a second memory portion;
circuitry configured, in response to receiving a command to perform a first operation at the first memory portion, to:
perform the first operation at the first memory portion,
perform a second operation of a different kind than the first operation, the second operation comprising a mode register read operation, and
provide on-die termination at the second portion during at least a portion of performing the mode register read operation.
9. The memory system of claim 8 , wherein the first operation is a refresh operation.
10. The memory device of claim 8 , wherein the command includes a flag bit indicating that the mode register read operation is to be performed.
11. The memory device of claim 8 , wherein the command includes a flag bit indicating to the second portion of the memory system that the on-die termination is to be provided.
12. The memory device of claim 8 , wherein the mode register read operation includes outputting from the memory system data from a mode register of the second memory portion.
13. The memory device of claim 12 , wherein the outputted data includes information corresponding to a temperature of the memory system.
14. The memory device of claim 12 , wherein the outputted data includes information corresponding to a refresh rate of the memory system.
15. The memory device of claim 8 , wherein the command has a duration on a command/address bus of the memory system of a single clock cycle of the memory system.
16. A memory system, comprising:
a memory device; and
a host device operably coupled to the memory device and including circuitry configured to:
send a command instructing the memory device to perform a first operation;
in response to the command to perform the first operation, receiving data output from the memory device in response to a second operation performed by the memory device, the second operation being different from the first operation, the second operation comprising a mode register read operation.
17. The memory system of claim 16 , wherein the first operation is a refresh operation.