Semiconductor devices including channel regions having non-uniform Ge concentration
In a method of manufacturing a semiconductor device including a Fin FET, a fin structure, which has an upper fin structure made of SiGe and a bottom fin structure made of a different material than the upper fin structure, is formed, a cover layer is formed over the fin structure, a thermal operation is performed on the fin structure covered by the cover layer, and a source/drain epitaxial layer is formed in a source/drain region of the upper fin structure. The thermal operation changes a germanium distribution in the upper fin structure.
1. A semiconductor device, comprising:
a fin structure having a channel region and a source/drain region;
a gate structure including a gate dielectric layer over the channel region and a gate electrode over the gate dielectric layer; and
a source/drain epitaxial layer formed in the source/drain region, wherein the channel region includes SiGe having a non-uniform Ge concentration that has a peak at a depth from a surface of the channel region and gradually and continuously decreases from the depth toward a center of the channel region, and wherein the Ge concentration at the surface of the channel region is in a range from 5 atomic % to 15 atomic %.
2. The semiconductor device of claim 1 , wherein the depth from the surface of the channel region is in a range from 1 nm to 5 nm.
3. The semiconductor device of claim 2 , wherein the Ge concentration at the peak is in a range from 30 atomic % to 40 atomic %.
4. The semiconductor device of claim 2 , wherein a lowest Ge concentration in the channel region is in a range from 10 atomic % to 25 atomic %.
5. The semiconductor device of claim 2 , wherein a difference between a highest Ge concentration and a lowest Ge concentration in the channel region is in a range from 5 to 35 by points of percent.
6. The semiconductor device of claim 1 , further comprising an isolation insulating layer from which the fin structure protrudes.
7. The semiconductor device of claim 6 , wherein:
the fin structure includes a fin bottom structure and an upper fin portion including the channel region, and
the fin bottom structure is made of a different semiconductor material than the upper fin portion.
8. The semiconductor device of claim 7 , comprising a liner layer disposed on side faces of the fin bottom structure.
9. The semiconductor device of claim 8 , wherein the liner layer covers a bottom portion of the upper fin portion.
10. The semiconductor device of claim 6 , wherein a width of the channel along a gate extending direction at a level of an upper surface of the isolation insulating layer is in a range from 15 nm to 30 nm.
11. The semiconductor device of claim 1 , wherein the Ge concentration has two peaks.
12. The semiconductor device of claim 8 , wherein the liner layer includes one or more layers of silicon oxide, silicon nitride, SiON, SiCN and SiOCN.
13. A semiconductor device, comprising:
a fin structure having a channel region and a source/drain region;
a gate structure including a gate dielectric layer over the channel region and a gate electrode over the gate dielectric layer; and
a source/drain epitaxial layer formed in the source/drain region,
wherein the channel region includes a SiGe layer having a non-uniform Ge concentration that has a peak at a depth from a surface of the channel region and gradually and continuously decreases from the depth toward a center of the channel region and a cap semiconductor layer over the SiGe layer, and wherein the Ge concentration at the surface of the channel region is in a range from 5 atomic % to 15 atomic %.
14. The semiconductor device of claim 13 , wherein the depth from the surface of the channel region is in a range from 1 nm to 5 nm.
15. The semiconductor device of claim 13 , wherein the Ge concentration at the peak is in a range from 30 atomic % to 40 atomic %.
16. The semiconductor device of claim 13 , wherein the Ge concentration at the peak is higher than a Ge concentration in the cap semiconductor layer.
17. The semiconductor device of claim 13 , wherein a difference between a highest Ge concentration and a lowest Ge concentration in the channel region is in a range from 5 to 35 by points of percent.
18. A semiconductor device, comprising:
a fin structure having a fin bottom structure and an upper fin portion including a channel region and a source/drain region;
an isolation insulating layer from which the channel region protrudes;
a gate structure including a gate dielectric layer over the channel region and a gate electrode over the gate dielectric layer; and
a source/drain epitaxial layer formed in the source/drain region,
wherein the channel region includes a SiGe layer having a non-uniform Ge concentration that has a peak at a depth from a surface of the channel region and gradually and continuously decreases from the depth toward a center of the channel region, and wherein the Ge concentration at the surface of the channel region is in a range from 5 atomic % to 15 atomic %.
19. The semiconductor device of claim 18 , the depth from the surface of the channel region is in a range from 1 nm to 5 nm.
20. The semiconductor device of claim 18 , wherein the Ge concentration at the peak is in a range from 30 atomic % to 40 atomic %.
21. The semiconductor device of claim 18 , wherein a lowest Ge concentration in the channel region is in a range from 10 atomic % to 25 atomic %.