Self-aligned spacers for multi-gate devices and method of fabrication thereof
A semiconductor device includes a substrate, a channel member above the substrate, a gate structure engaging the channel member, an epitaxial feature in physical contact with the channel member, and a dielectric layer interposing the gate structure and the epitaxial feature. A sidewall surface of the dielectric layer facing the gate structure has a convex shape in a top view, and the convex shape has a center portion extending towards the gate structure.
1. A semiconductor device, comprising:
a substrate;
a channel member above the substrate;
a gate structure engaging the channel member;
an epitaxial feature in physical contact with the channel member; and
a dielectric layer interposing the gate structure and the epitaxial feature, wherein a sidewall surface of the dielectric layer facing the gate structure has a convex shape in a top view, and the convex shape has a center portion extending towards the gate structure.
2. The semiconductor device of claim 1 , wherein the sidewall surface of the dielectric layer facing the gate structure has a concave shape in a side view, and the concave shape has a center portion extending away from the gate structure.
3. The semiconductor device of claim 2 , wherein the concave shape has a depth measured from the center portion to an edge of the concave shape ranging from about 0.5 nm to about 5 nm along a lengthwise direction of the channel member.
4. The semiconductor device of claim 1 , wherein the convex shape has a distance measured from the center portion to an edge of the convex shape ranging from about 0.5 nm to about 5 nm along a lengthwise direction of the channel member.
5. The semiconductor device of claim 1 , wherein another sidewall surface of the dielectric layer facing the epitaxial feature is substantially straight in both the top view and a side view.
6. The semiconductor device of claim 1 , wherein a portion of the dielectric layer is directly under the epitaxial feature.
7. The semiconductor device of claim 6 , wherein the portion of the dielectric layer separates the epitaxial feature from physically contacting the substrate.
8. The semiconductor device of claim 1 , further comprising:
a gate spacer disposed on sidewalls of the gate structure, wherein the convex shape intersects a sidewall of the gate spacer in the top view.
9. The semiconductor device of claim 8 , wherein the sidewall of the gate spacer extends along a lengthwise direction of the channel member in the top view.
10. The semiconductor device of claim 1 , wherein the dielectric layer includes a dielectric material selected from the group of SiN, SiOC, SiCN, and SiO 2 .
11. A semiconductor device, comprising:
a channel member above a substrate;
a gate structure engaging the channel member;
an epitaxial feature in physical contact with the channel member; and
a dielectric layer interposing the gate structure and the epitaxial feature, wherein a portion of the dielectric layer extends directly under the epitaxial feature and separates the epitaxial feature from physically contacting the substrate.
12. The semiconductor device of claim 11 , wherein the gate structure has a first portion that is under a bottommost surface of the epitaxial feature.
13. The semiconductor device of claim 12 , wherein the gate structure has a second portion above the channel member, and wherein the first portion is wider than the second portion along a lengthwise direction of the channel member.
14. The semiconductor device of claim 11 , wherein the dielectric layer includes a sidewall interfacing the gate structure, and the sidewall has a middle portion bends away from the gate structure in a side view.
15. The semiconductor device of claim 11 , wherein the dielectric layer includes a sidewall interfacing the gate structure, and the sidewall has a middle portion protruding towards the gate structure in a top view.
16. The semiconductor device of claim 11 , further comprising:
a gate spacer disposed on sidewalls of the gate structure, wherein the portion of the dielectric layer extends laterally beyond a sidewall of the gate spacer.
17. A semiconductor device, comprising:
a substrate;
a plurality of nanosheets vertically stacked over each other and above the substrate;
a gate structure surrounding each of the nano sheets;
an epitaxial source/drain (S/D) feature abutting the nanosheets; and
an inner spacer layer sandwiched between the epitaxial S/D feature and the gate structure, wherein a portion of the inner spacer layer is directly under a bottommost surface of the epitaxial S/D feature.
18. The semiconductor device of claim 17 , wherein the portion of the inner spacer layer separates the epitaxial S/D feature from physically contacting the substrate.
19. The semiconductor device of claim 17 , wherein the inner spacer layer has a straight sidewall interfacing the epitaxial S/D feature and a curvature sidewall interfacing the gate structure.
20. The semiconductor device of claim 19 , wherein the curvature sidewall bends away from the gate structure in a side view.