Semiconductor element memory device
View Patent ↗A memory device according to the present invention includes memory cells, each of the memory cells includes a semiconductor base material that is formed on a substrate and that stands on the substrate in a vertical direction, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer in each of the memory cells are controlled to perform a write operation of retaining, inside a channel semiconductor layer, a group of positive holes generated by an impact ionization phenomenon or by a gate-induced drain leakage current, and the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer are controlled to perform an erase operation of discharging the group of positive holes from inside the channel semiconductor layer. The first gate conductor layer partially surrounds a side surface of the semiconductor base material, and the second gate conductor layer entirely surrounds the side surface of the semiconductor base material.
1. A semiconductor memory device comprising a plurality of memory cells arranged in a matrix arranged in a column direction and a line direction, each of the memory cells comprising:
a columnar semiconductor base material formed to stand on a substrate in a vertical direction or to extend in a horizontal direction along the substrate, the columnar semiconductor base having a length in a longitudinal direction with first and a second longitudinal ends, wherein the columnar semiconductor base includes a columnar channel semiconductor layer between the first and second longitudinal ends that has a first section and a second section arranged in series in the longitudinal direction along the columnar channel semiconductor layer;
a first impurity layer and a second impurity layer formed, respectively, at the first and second longitudinal ends of the columnar semiconductor base material;
a first gate insulating layer formed in contact with or in a close vicinity to the first impurity layer, wherein the first gate insulating layer is formed to at least partially, circumferentially surround the first section of the columnar channel semiconductor layer between the first impurity layer and the second impurity layer;
a second gate insulating layer formed in contact with or in a close vicinity to the second impurity layer, wherein the second gate insulating layer is formed to entirely, circumferentially surround the second section of the columnar channel semiconductor layer;
a first gate conductor layer formed around the first gate insulating layer to only partially, circumferentially surround the first section of the columnar channel semiconductor layer; and
a second gate conductor layer formed around the second gate insulating layer to entirely, circumferentially surround the second section of the columnar channel semiconductor layer, wherein the first and second gate conductor layers are arranged in series along the longitudinal direction;
wherein in each memory cell, voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer are controlled to perform a write operation, an erase operation, and a read operation,
the first impurity layer of the memory cell is connected to a source line wiring layer, the second impurity layer thereof is connected to a bit line wiring layer, the first gate conductor layer thereof is connected to a first driving control line wiring layer, and the second gate conductor layer thereof is connected to a word line wiring layer, and
the first driving control line wiring layer and the word line wiring layer are disposed parallel to a row direction.
2. The semiconductor element memory device according to claim 1 , wherein the first driving control line wiring layer is formed in common for the semiconductor base materials of the memory cells that are formed adjacent to each other in the column direction.
3. The semiconductor element memory device according to claim 1 , wherein the first gate insulating layer has a longitudinal length shorter than a longitudinal length of the second gate insulating layer.
4. The semiconductor element memory device according to claim 1 , wherein a first gate capacitance between the first gate conductor layer and the channel semiconductor layer is made larger than a second gate capacitance between the second gate conductor layer and the channel semiconductor layer.
5. The semiconductor element memory device according to claim 1 , wherein in the write operation, a group of positive holes generated by an impact ionization phenomenon or by a gate-induced drain leakage current are retained inside the channel semiconductor layer, and a voltage of the channel semiconductor layer is made equal to a first data retention voltage that is higher than the voltage of either the first impurity layer or the second impurity layer or that is higher than the voltages of both the first impurity layer and the second impurity layer, and
in the erase operation, the voltages applied to the first impurity layer, the second impurity layer, the first gate conductor layer, and the second gate conductor layer are controlled to discharge the group of positive holes through either the first impurity layer or the second impurity layer or both the first impurity layer and the second impurity layer, and the voltage of the channel semiconductor layer is made equal to a second data retention voltage that is lower than the first data retention voltage.