Dislocation enhanced transistor device and method
Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include transistors formed in a (100) surface of a semiconductor substrate wherein a channel is oriented in a <100> direction. The transistors further include one or more strain induced dislocations adjacent to a channel.
1. A transistor, comprising:
a source region and a drain region separated by a channel and formed in a (100) surface of a semiconductor substrate wherein the channel is oriented in a <100> direction;
a gate dielectric over the channel;
a gate over the gate dielectric;
one or more strain induced dislocations adjacent to the channel.
2. The transistor of claim 1 , wherein the one or more strain induced dislocations are located at edges of the channel.
3. The transistor of claim 1 , further including one or more cap layers over the gate.
4. The transistor of claim 3 , wherein the one or more cap layers include a silicon nitride layer.
5. The transistor of claim 3 , wherein the one or more cap layers include a silicon oxide layer adjacent to the gate and a silicon nitride layer over the silicon oxide layer.
6. The transistor of claim 1 , wherein a strain within the channel is greater than or equal to 0.2 percent.
7. The transistor of claim 1 , wherein a strain within the channel is greater than or equal to 0.2 percent in a direction parallel with the channel.
8. The transistor of claim 1 , wherein a strain within the channel is greater than or equal to 0.2 percent in a direction perpendicular to the channel.
9. The transistor of claim 1 , wherein the channel is an N-type channel.
10. A memory device, comprising:
a plurality of PMOS and NMOS devices formed in a (100) surface of a semiconductor substrate wherein channels of the PMOS and NMOS devices are oriented in a <100> direction;
a number of gate dielectrics over the channels;
a number of gates over the gate dielectrics;
one or more strain induced dislocations adjacent to N-channels of the NMOS devices.
11. The memory device of claim 10 , further including one or more cap layers over the number of gates.
12. The memory device of claim 11 , wherein the one or more cap layers include a silicon nitride layer.
13. The memory device of claim 11 , wherein the one or more cap layers include a silicon oxide layer adjacent to the gate and a silicon nitride layer over the silicon oxide layer.
14. The memory device of claim 10 , wherein a strain within the channel is greater than or equal to 0.2 percent.
15. The memory device of claim 10 , wherein a strain within the channel is greater than or equal to 0.2 percent in a direction parallel with the channel.
16. The memory device of claim 10 , wherein a strain within the channel is greater than or equal to 0.2 percent in a direction perpendicular to the channel.