Shift register unit, gate driving circuit, display device, and driving method

1. A shift register unit, comprising a first input circuit, an output control circuit, an output circuit, a fourth node control circuit, and a second noise reduction circuit;

wherein the first input circuit is connected to a first node, and is configured to output a first input signal to the first node in response to a first control signal, wherein the first input signal is a constant high level signal;

the output control circuit is connected to the first node and a second node, and is configured to output an output control signal to the second node;

the output circuit comprises an output terminal, and the output circuit is connected to the second node, and is configured to output an output signal to the output terminal under control of a level of the second node;

the fourth node control circuit is connected to the second node and a fourth node, and is configured to control a level of the fourth node under control of the level of the second node; and

the second noise reduction circuit is connected to the second node, the fourth node, and the output terminal, and is configured to perform noise reduction on the second node and the output terminal under control of the level of the fourth node;

wherein the output terminal comprises a shift output terminal and at least one scan signal output terminal;

wherein the at least one scan signal output terminal comprises a first scan signal output terminal and a second scan signal output terminal, and the second noise reduction circuit comprises an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a fourteenth transistor;

a gate electrode of the eleventh transistor is connected to the fourth node, a first electrode of the eleventh transistor is connected to the second node, and a second electrode of the eleventh transistor is connected to a second voltage terminal to receive a second voltage;

a gate electrode of the twelfth transistor is connected to the fourth node, a first electrode of the twelfth transistor is connected to the shift output terminal, and a second electrode of the twelfth transistor is connected to the second voltage terminal to receive the second voltage;

a gate electrode of the thirteenth transistor is connected to the fourth node, a first electrode of the thirteenth transistor is connected to the first scan signal output terminal, and a second electrode of the thirteenth transistor is connected to a third voltage terminal to receive a third voltage; and

a gate electrode of the fourteenth transistor is connected to the fourth node, a first electrode of the fourteenth transistor is connected to the second scan signal output terminal, and a second electrode of the fourteenth transistor is connected to the third voltage terminal to receive the third voltage,

wherein the output circuit comprises a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, and a second capacitor;

a gate electrode of the fifteenth transistor is connected to the second node, a first electrode of the fifteenth transistor is connected to a fourth clock signal terminal to receive a fourth clock signal as the output signal, and a second electrode of the fifteenth transistor is connected to the shift output terminal;

a gate electrode of the sixteenth transistor is connected to the second node, and a first electrode of the sixteenth transistor is connected to the fourth clock signal terminal to receive the fourth clock signal as the output signal, and a second electrode of the sixteenth transistor is connected to the first scan signal output terminal;

a gate electrode of the seventeenth transistor is connected to the second node, and a first electrode of the seventeenth transistor is connected to a fifth clock signal terminal to receive a fifth clock signal as the output signal, and a second electrode of the seventeenth transistor is connected to the second scan signal output terminal; and

a first terminal of the second capacitor is connected to the second node, and a second terminal of the second capacitor is connected to the shift output terminal,

wherein the shift register unit further comprises a second input circuit;

the second input circuit is connected to the first node, and is configured to input a second input signal according to a second control signal;

the second input circuit comprises a charging sub-circuit, a storage sub-circuit, and an isolation sub-circuit;

the charging sub-circuit is connected to a blanking node, and is configured to input the second control signal to the blanking node in response to a sixth clock signal;

the storage sub-circuit is connected to the blanking node, and is configured to store a level of the second control signal input by the charging sub-circuit; and

the isolation sub-circuit is connected to the blanking node and the first node, and is configured to input the second input signal under control of a level of the blanking node and a seventh clock signal;

the charging sub-circuit comprises an eighteenth transistor, a gate electrode of the eighteenth transistor is connected to a sixth clock signal terminal to receive the sixth clock signal, a first electrode of the eighteenth transistor is connected to a blanking control terminal to receive the second control signal, and a second electrode of the eighteenth transistor is connected to the blanking node;

the storage sub-circuit comprises a third capacitor, a first terminal of the third capacitor is connected to the blanking node, and is configured to store a level of the second control signal; and

the isolation sub-circuit comprises a nineteenth transistor and a twentieth transistor, and a gate electrode of the twentieth transistor is connected to a seventh clock signal terminal to receive the seventh clock signal, a first electrode of the twentieth transistor is connected to a second electrode of the nineteenth transistor, and a second electrode of the twentieth transistor is connected to the first node.

2. The shift register unit according to claim 1 , further comprising a third node control circuit, wherein the third node control circuit is connected to the first node and a third node, and is configured to control a level of the third node under control of the level of the first node.

3. The shift register unit according to claim 2 , further comprising a first noise reduction circuit, wherein the first noise reduction circuit is connected to the first node and the second node and is configured to perform noise reduction on the second node.

4. The shift register unit according to claim 1 , wherein the first input circuit comprises a first transistor, a gate electrode of the first transistor is connected to a display control terminal to receive the first control signal, a first electrode of the first transistor is connected to a first voltage terminal to receive a first voltage as the first input signal, and a second electrode of the first transistor is connected to the first node.

5. The shift register unit according to claim 2 , wherein the third node control circuit comprises a second transistor, a third transistor, and a fourth transistor;

a gate electrode and a first electrode of the second transistor are connected to each other, and are connected to a first clock signal terminal to receive a first clock signal, and a second electrode of the second transistor is connected to the third node;

a gate electrode and a first electrode of the third transistor are connected to each other, and are connected to a second clock signal terminal to receive a second clock signal, and a second electrode of the third transistor is connected to the third node; and

a gate electrode of the fourth transistor is connected to the first node, a first electrode of the fourth transistor is connected to the third node, and a second electrode of the fourth transistor is connected to the second voltage terminal to receive the second voltage.

6. The shift register unit according to claim 3 , wherein the first noise reduction circuit comprises a fifth transistor and a sixth transistor;

a first electrode of the fifth transistor is connected to the first node, and a second electrode of the fifth transistor is connected to the second voltage terminal to receive the second voltage; and

a first electrode of the sixth transistor is connected to the second node, and a second electrode of the sixth transistor is connected to the second voltage terminal to receive the second voltage.

7. The shift register unit according to claim 1 , wherein the output control circuit comprises a seventh transistor configured to output an input control signal to the second node.

8. The shift register unit according to claim 1 , wherein the fourth node control circuit comprises an eighth transistor and a tenth transistor;

a gate electrode and a first electrode of the eighth transistor are connected to each other, and are connected to a first clock signal terminal to receive a first clock signal, and a second electrode of the eighth transistor is connected to the fourth node; and

a gate electrode of the tenth transistor is connected to the second node, a first electrode of the tenth transistor is connected to the fourth node, and a second electrode of the tenth transistor is connected to the second voltage terminal to receive the second voltage.

9. The shift register unit according to claim 1 , further comprising a display reset circuit,

wherein the display reset circuit is connected to the first node, and is configured to reset the first node in response to a display reset signal;

the display reset circuit comprises a twenty-first transistor; and

a gate electrode of the twenty-first transistor is connected to a display reset terminal to receive the display reset signal, a first electrode of the twenty-first transistor is connected to the first node, and a second electrode of the twenty-first transistor is connected to the second voltage terminal to receive the second voltage.

10. The shift register unit according to claim 1 , further comprising a blanking reset circuit,

wherein the blanking reset circuit is connected to the first node, and is configured to reset the output control circuit in response to a blanking reset signal;

the blanking reset circuit comprises a twenty-second transistor; and

a first electrode of the twenty-second transistor is connected to the first node, and a second electrode of the twenty-second transistor is connected to the second voltage terminal to receive the second voltage.

11. The shift register unit according to claim 1 , further comprising a third node control circuit,

wherein the first input circuit comprises a first transistor, a gate electrode of the first transistor is connected to a display control terminal to receive the first control signal, a first electrode of the first transistor is connected to a first voltage terminal to receive a first voltage as the first input signal, and a second electrode of the first transistor is connected to the first node;

the third node control circuit comprises a second transistor, a third transistor, and a fourth transistor, a gate electrode and a first electrode of the second transistor are connected to each other and are connected to a first clock signal terminal to receive a first clock signal, a second electrode of the second transistor is connected to a third node, a gate electrode and a first electrode of the third transistor are connected to each other and are connected to a second clock signal terminal to receive a second clock signal, a second electrode of the third transistor is connected to the third node, a gate electrode of the fourth transistor is connected to the first node, a first electrode of the fourth transistor is connected to the third node, and a second electrode of the fourth transistor is connected to the second voltage terminal to receive the second voltage; and

the output control circuit comprises a seventh transistor, configured to output the output control signal to the second node.

12. A gate driving circuit, comprising a plurality of cascaded shift register units according to claim 1 .

13. A display device, comprising the gate driving circuit according to claim 12 .

14. A driving method for driving the shift register unit according to claim 1 , comprising:

in response to the first control signal, inputting the first input signal to the first node through the first input circuit;

outputting the output control signal to the second node; and

outputting the output signal to the output terminal under control of the level of the second node.

15. The shift register unit according to claim 4 , wherein a display control terminal of a first stage of shift register unit and a display control terminal of a second stage of shift register unit are connected, to receive a trigger signal, and a display control terminal of an (n+2)-th stage of shift register unit is connected to a shift output terminal of an n-th stage of shift register unit, wherein n is an integer and is larger than 1.

16. The shift register unit according to claim 4 , wherein the gate electrode of the first transistor is connected to the first electrode of the first transistor.

17. A shift register unit, comprising a first input circuit, an output control circuit, an output circuit, a fourth node control circuit, a third node control circuit, a first noise reduction circuit, and a second noise reduction circuit, and a display reset circuit, wherein

the first input circuit comprises a first transistor, a first electrode of the first transistor is connected to a first voltage terminal to receive a first voltage as a first input signal, the first voltage is a constant high level signal, and a second electrode of the first transistor is connected to a first node;

the third node control circuit comprises a second transistor, a third transistor, and a fourth transistor, a first electrode of the second transistor is connected to a first clock signal terminal to receive a first clock signal, and a second electrode of the second transistor is connected to a third node; a first electrode of the third transistor is connected to a second clock signal terminal to receive a second clock signal, and a second electrode of the third transistor is connected to the third node; a first electrode of the fourth transistor is connected to the third node, and a second electrode of the fourth transistor is connected to a second voltage terminal to receive a second voltage;

the first noise reduction circuit comprises a fifth transistor and a sixth transistor; a first electrode of the fifth transistor is connected to the first node, and a second electrode of the fifth transistor is connected to the second voltage terminal to receive the second voltage; and a first electrode of the sixth transistor is connected to a second node, and a second electrode of the sixth transistor is connected to the second voltage terminal to receive the second voltage;

the output control circuit comprises a seventh transistor configured to output an input control signal to the second node;

the fourth node control circuit comprises an eighth transistor, and a tenth transistor; a first electrode of the eighth transistor is connected to the first clock signal terminal to receive the first clock signal, and a second electrode of the eighth transistor is connected to a fourth node; a first electrode of the tenth transistor is connected to the fourth node, and a second electrode of the tenth transistor is connected to the second voltage terminal to receive the second voltage;

the second noise reduction circuit comprises an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a fourteenth transistor; a first electrode of the eleventh transistor is connected to the second node, and a second electrode of the eleventh transistor is connected to the second voltage terminal to receive the second voltage; a first electrode of the twelfth transistor is connected to a shift output terminal, and a second electrode of the twelfth transistor is connected to the second voltage terminal to receive the second voltage; a first electrode of the thirteenth transistor is connected to a first scan signal output terminal, and a second electrode of the thirteenth transistor is connected to a third voltage terminal to receive a third voltage; a first electrode of the fourteenth transistor is connected to a second scan signal output terminal, and a second electrode of the fourteenth transistor is connected to the third voltage terminal to receive the third voltage; and

the output circuit comprises a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, and a second capacitor; a first electrode of the fifteenth transistor is connected to a fourth clock signal terminal to receive a fourth clock signal as an output signal, and a second electrode of the fifteenth transistor is connected to the shift output terminal; a first electrode of the sixteenth transistor is connected to the fourth clock signal terminal to receive the fourth clock signal as an output signal, and a second electrode of the sixteenth transistor is connected to the first scan signal output terminal; and a first electrode of the seventeenth transistor is connected to a fifth clock signal terminal to receive a fifth clock signal as an output signal, and a second electrode of the seventeenth transistor is connected to the second scan signal output terminal; and a first terminal of the second capacitor is connected to the second node, and a second terminal of the second capacitor is connected to the shift output terminal;

a gate electrode of the fifteenth transistor is connected to the second node;

a gate electrode of the sixteenth transistor is connected to the second node, and a first electrode of the sixteenth transistor is connected to the fourth clock signal terminal to receive the fourth clock signal as the output signal, and a second electrode of the sixteenth transistor is connected to the first scan signal output terminal;

a gate electrode of the seventeenth transistor is connected to the second node,

wherein the shift register unit further comprises a second input circuit;

the second input circuit is connected to the first node, and is configured to input a second input signal according to a second control signal;

the second input circuit comprises a charging sub-circuit, a storage sub-circuit, and an isolation sub-circuit;

the charging sub-circuit is connected to a blanking node, and is configured to input the second control signal to the blanking node in response to a sixth clock signal;

the storage sub-circuit is connected to the blanking node, and is configured to store a level of the second control signal input by the charging sub-circuit; and

the isolation sub-circuit is connected to the blanking node and the first node, and is configured to input the second input signal under control of a level of the blanking node and a seventh clock signal;

the charging sub-circuit comprises an eighteenth transistor, a gate electrode of the eighteenth transistor is connected to a sixth clock signal terminal to receive the sixth clock signal, a first electrode of the eighteenth transistor is connected to a blanking control terminal to receive the second control signal, and a second electrode of the eighteenth transistor is connected to the blanking node;

the storage sub-circuit comprises a third capacitor, a first terminal of the third capacitor is connected to the blanking node, and is configured to store a level of the second control signal; and

the isolation sub-circuit comprises a nineteenth transistor and a twentieth transistor, and a gate electrode of the twentieth transistor is connected to a seventh clock signal terminal to receive the seventh clock signal, a first electrode of the twentieth transistor is connected to a second electrode of the nineteenth transistor, and a second electrode of the twentieth transistor is connected to the first node.

18. The shift register unit according to claim 17 , further comprising a blanking reset circuit, the blanking reset circuit comprises a twenty-second transistor; and

a first electrode of the twenty-second transistor is connected to the first node, and a second electrode of the twenty-second transistor is connected to the second voltage terminal to receive the second voltage.

19. A shift register unit, comprising a first input circuit, a second input circuit, an output control circuit, an output circuit, a fourth node control circuit, a third node control circuit, a first noise reduction circuit, and a second noise reduction circuit, and a display reset circuit, wherein

the first input circuit comprises a first transistor, a first electrode of the first transistor is connected to a first voltage terminal to receive a first voltage as a first input signal, the first voltage is a constant high level signal, and a second electrode of the first transistor is connected to a first node;

the third node control circuit comprises a second transistor, a third transistor, and a fourth transistor, a first electrode of the second transistor is connected to a first clock signal terminal to receive a first clock signal, and a second electrode of the second transistor is connected to a third node; a first electrode of the third transistor is connected to a second clock signal terminal to receive a second clock signal, and a second electrode of the third transistor is connected to the third node; a first electrode of the fourth transistor is connected to the third node, and a second electrode of the fourth transistor is connected to a second voltage terminal to receive a second voltage;

the first noise reduction circuit comprises a fifth transistor and a sixth transistor; a first electrode of the fifth transistor is connected to the first node, and a second electrode of the fifth transistor is connected to the second voltage terminal to receive the second voltage; and a first electrode of the sixth transistor is connected to a second node, and a second electrode of the sixth transistor is connected to the second voltage terminal to receive the second voltage;

the output control circuit comprises a seventh transistor configured to output an input control signal to the second node;

the fourth node control circuit comprises an eighth transistor, and a tenth transistor; a first electrode of the eighth transistor is connected to the first clock signal terminal to receive the first clock signal, and a second electrode of the eighth transistor is connected to a fourth node; a first electrode of the tenth transistor is connected to the fourth node, and a second electrode of the tenth transistor is connected to the second voltage terminal to receive the second voltage;

the second noise reduction circuit comprises an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a fourteenth transistor; a first electrode of the eleventh transistor is connected to the second node, and a second electrode of the eleventh transistor is connected to the second voltage terminal to receive the second voltage; a first electrode of the twelfth transistor is connected to a shift output terminal, and a second electrode of the twelfth transistor is connected to the second voltage terminal to receive the second voltage; a first electrode of the thirteenth transistor is connected to a first scan signal output terminal, and a second electrode of the thirteenth transistor is connected to a third voltage terminal to receive a third voltage; a first electrode of the fourteenth transistor is connected to a second scan signal output terminal, and a second electrode of the fourteenth transistor is connected to the third voltage terminal to receive the third voltage;

the output circuit comprises a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, and a second capacitor; a first electrode of the fifteenth transistor is connected to a fourth clock signal terminal to receive a fourth clock signal as an output signal, and a second electrode of the fifteenth transistor is connected to the shift output terminal; a first electrode of the sixteenth transistor is connected to the fourth clock signal terminal to receive the fourth clock signal as an output signal, and a second electrode of the sixteenth transistor is connected to the first scan signal output terminal; and a first electrode of the seventeenth transistor is connected to a fifth clock signal terminal to receive a fifth clock signal as an output signal, and a second electrode of the seventeenth transistor is connected to the second scan signal output terminal; and a first terminal of the second capacitor is connected to the second node, and a second terminal of the second capacitor is connected to the shift output terminal;

the second input circuit comprises an eighteenth transistor, a nineteenth transistor and a twentieth transistor, a first electrode of the eighteenth transistor is connected to a blanking control terminal to receive a second control signal, and a second electrode of the eighteenth transistor is connected to a blanking node; a first electrode of the twentieth transistor is connected to a second electrode of the nineteenth transistor, and a second electrode of the twentieth transistor is connected to the first node; and

the display reset circuit comprises a twenty-first transistor, a first electrode of the twenty-first transistor is connected to the first node, and a second electrode of the twenty-first transistor is connected to the second voltage terminal to receive the second voltage;

a gate electrode of the fifteenth transistor is connected to the second node;

a gate electrode of the sixteenth transistor is connected to the second node, and a first electrode of the sixteenth transistor is connected to the fourth clock signal terminal to receive the fourth clock signal as the output signal, and a second electrode of the sixteenth transistor is connected to the first scan signal output terminal;

a gate electrode of the seventeenth transistor is connected to the second node;

the second input circuit is connected to the first node, and is configured to input a second input signal according to the second control signal;

the second input circuit comprises a charging sub-circuit, a storage sub-circuit, and an isolation sub-circuit;

the charging sub-circuit is connected to the blanking node, and is configured to input the second control signal to the blanking node in response to a sixth clock signal;

the storage sub-circuit is connected to the blanking node, and is configured to store a level of the second control signal input by the charging sub-circuit; and

the isolation sub-circuit is connected to the blanking node and the first node, and is configured to input the second input signal under control of a level of the blanking node and a seventh clock signal;

the charging sub-circuit comprises the eighteenth transistor, a gate electrode of the eighteenth transistor is connected to a sixth clock signal terminal to receive the sixth clock signal;

the storage sub-circuit comprises a third capacitor, a first terminal of the third capacitor is connected to the blanking node, and is configured to store a level of the second control signal; and

the isolation sub-circuit comprises the nineteenth transistor and the twentieth transistor, and a gate electrode of the twentieth transistor is connected to a seventh clock signal terminal to receive the seventh clock signal.

20. The shift register unit according to claim 19 , further comprising a blanking reset circuit, the blanking reset circuit comprises a twenty-second transistor; and

a first electrode of the twenty-second transistor is connected to the first node, and a second electrode of the twenty-second transistor is connected to the second voltage terminal to receive the second voltage.