Hardware Encoder for Color Data in a 2D Rendering Pipeline

1 . A method comprising, by a hardware encoder:

receiving a plurality of blocks of pixels of an image, wherein the blocks are to be sequentially encoded using a hardware-encoding pipeline;

encoding a first block of the plurality of blocks by:

generating a first hash to represent the first block;

identifying a second hash stored in memory matching the first hash, the second hash (i) representing a second block of the plurality of blocks previously processed by the hardware-encoding pipeline and (ii) is associated with a tag corresponding to a placeholder for a second header associated with the second block;

passing a copy of the tag through the hardware-encoding pipeline as metadata for the first block;

determining that the second header is available;

replacing the copy of the tag with the second header to generate a first encoding for the first block, wherein the second header specifies a memory region where a second encoding of the second block is stored.

2 . The method of claim 1 , wherein the plurality of blocks that are to be sequentially encoded using the hardware-encoding pipeline are arranged in a particular sequence.

3 . The method of claim 2 , wherein the plurality of blocks are arranged in the particular sequence based on Morton Order.

4 . The method of claim 2 , wherein identifying the second hash stored in memory matching the first hash comprises:

comparing the first hash to a plurality of hashes stored in memory; and

identifying the second hash amongst the plurality of hashes that matches the first hash.

5 . The method of claim 4 , wherein the plurality of hashes stored in memory correspond to a fixed number of blocks of the plurality of blocks previously processed according to the particular sequence.

6 . The method of claim 4 , wherein the plurality of hashes are stored in memory according to a first-in-first-out (FIFO) protocol.

7 . The method of claim 1 , wherein encoding the first block of the plurality of blocks does not involve encoding pixel data associated with the first block.

8 . One or more computer-readable non-transitory storage media including instructions that, when executed by a hardware encoder, are configured to cause the one or more processors to:

receive a plurality of blocks of pixels of an image, wherein the blocks are to be sequentially encoded using a hardware-encoding pipeline;

encode a first block of the plurality of blocks by:

generating a first hash to represent the first block;

identifying a second hash stored in memory matching the first hash, the second hash (i) representing a second block of the plurality of blocks previously processed by the hardware-encoding pipeline and (ii) is associated with a tag corresponding to a placeholder for a second header associated with the second block;

passing a copy of the tag through the hardware-encoding pipeline as metadata for the first block;

determining that the second header is available;

replacing the copy of the tag with the second header to generate a first encoding for the first block, wherein the second header specifies a memory region where a second encoding of the second block is stored.

9 . The one or more computer-readable non-transitory storage media of claim 8 , wherein the plurality of blocks that are to be sequentially encoded using the hardware-encoding pipeline are arranged in a particular sequence.

10 . The one or more computer-readable non-transitory storage media of claim 9 , wherein the plurality of blocks are arranged in the particular sequence based on Morton Order.

11 . The one or more computer-readable non-transitory storage media of claim 9 , wherein identifying the second hash stored in memory matching the first hash comprises:

comparing the first hash to a plurality of hashes stored in memory; and

identifying the second hash amongst the plurality of hashes that matches the first hash.

12 . The one or more computer-readable non-transitory storage media of claim 11 , wherein the plurality of hashes stored in memory correspond to a fixed number of blocks of the plurality of blocks previously processed according to the particular sequence.

13 . The one or more computer-readable non-transitory storage media of claim 11 , wherein the plurality of hashes are stored in memory according to a first-in-first-out (FIFO) protocol.

14 . The one or more computer-readable non-transitory storage media of claim 8 , wherein encoding the first block of the plurality of blocks does not involve encoding pixel data associated with the first block.

15 . A hardware encoder comprising: one or more processors; and one or more computer-readable non-transitory storage media in communication with the one or more processors, the one or more computer-readable non-transitory storage media comprising instructions that when executed by the one or more processors, cause the hardware encoder to:

receive a plurality of blocks of pixels of an image, wherein the blocks are to be sequentially encoded using a hardware-encoding pipeline;

encode a first block of the plurality of blocks by:

generating a first hash to represent the first block;

identifying a second hash stored in memory matching the first hash, the second hash (i) representing a second block of the plurality of blocks previously processed by the hardware-encoding pipeline and (ii) is associated with a tag corresponding to a placeholder for a second header associated with the second block;

passing a copy of the tag through the hardware-encoding pipeline as metadata for the first block;

determining that the second header is available;

replacing the copy of the tag with the second header to generate a first encoding for the first block, wherein the second header specifies a memory region where a second encoding of the second block is stored.

16 . The hardware encoder of claim 15 , wherein the plurality of blocks that are to be sequentially encoded using the hardware-encoding pipeline are arranged in a particular sequence based on Morton Order.

17 . The hardware encoder of claim 16 , wherein identifying the second hash stored in memory matching the first hash comprises:

comparing the first hash to a plurality of hashes stored in memory; and

identifying the second hash amongst the plurality of hashes that matches the first hash.

18 . The hardware encoder of claim 17 , wherein the plurality of hashes stored in memory correspond to a fixed number of blocks of the plurality of blocks previously processed according to the particular sequence.

19 . The hardware encoder of claim 17 , wherein the plurality of hashes are stored in memory according to a first-in-first-out (FIFO) protocol.

20 . The hardware encoder of claim 15 , wherein encoding the first block of the plurality of blocks does not involve encoding pixel data associated with the first block.