Low-power high throughput hardware decoder with random block access
A method includes receiving a block comprising pixels; encoding the pixels by: arranging the pixels in a sequence; generating a delta encoding of the pixels, the delta encoding comprising (a) a base value and (b) delta values having non-zero delta values and zero delta values, each delta value representing a difference between a corresponding pixel in the sequence and a previous pixel in the sequence; generating a symbol mask indicating whether each of the delta values is zero or non-zero; determining, based on magnitudes of the non-zero delta values, a symbol width for encoding each of the non-zero delta values; generating a sequence of symbols that respectively encode the non-zero delta values using the symbol width; generating a compression of the block by collating the symbol mask, the symbol width, and the sequence of symbols.
1. A method comprising, by a computing system:
receiving a block comprising a plurality of pixels;
encoding the plurality of pixels by:
arranging the plurality of pixels in a sequence;
generating a delta encoding of the plurality of pixels, the delta encoding comprising (a) a base value and (b) a plurality of delta values having non-zero delta values and zero delta values, each delta value representing a difference between a corresponding pixel in the sequence and a previous pixel in the sequence;
generating a symbol mask indicating whether each of the plurality of delta values is zero or non-zero;
determining, based on magnitudes of the non-zero delta values, a symbol width for encoding each of the non-zero delta values;
generating a sequence of symbols that respectively encode the non-zero delta values using the symbol width;
generating a compression of the block by collating the symbol mask, the symbol width, and the sequence of symbols.
2. The method of claim 1 , wherein the plurality of pixels of the block correspond to a single channel of pixel values amongst a plurality channels of pixel values.
3. The method of claim 1 , wherein arranging the plurality of pixels in a sequence is based on Morton Order.
4. The method of claim 1 , further comprising:
determining that a bit length associated with the compression of the block is more than a bit length associated with the plurality of the pixels of the block as uncompressed; and
storing the plurality of pixels of the block as uncompressed.
5. The method of claim 1 , wherein the symbol width for encoding each of the non-zero delta values includes an offset.
6. The method of claim 1 , further comprising modifying the compression of the block to be byte-aligned by adding additional bits to the compression of the block.
7. The method of claim 1 , further comprising decoding the compression of the block by processing two or more delta values of the plurality of delta values in parallel.
8. One or more computer-readable non-transitory storage media including instructions that, when executed by one or more processors, are configured to cause the one or more processors to:
receive a block comprising a plurality of pixels;
encode the plurality of pixels by:
arranging the plurality of pixels in a sequence;
generating a delta encoding of the plurality of pixels, the delta encoding comprising (a) a base value and (b) a plurality of delta values having non-zero delta values and zero delta values, each delta value representing a difference between a corresponding pixel in the sequence and a previous pixel in the sequence;
generating a symbol mask indicating whether each of the plurality of delta values is zero or non-zero;
determining, based on magnitudes of the non-zero delta values, a symbol width for encoding each of the non-zero delta values;
generating a sequence of symbols that respectively encode the non-zero delta values using the symbol width;
generating a compression of the block by collating the symbol mask, the symbol width, and the sequence of symbols.
9. The one or more computer-readable non-transitory storage media of claim 8 , wherein the plurality of pixels of the block correspond to a single channel of pixel values amongst a plurality channels of pixel values.
10. The one or more computer-readable non-transitory storage media of claim 8 , wherein arranging the plurality of pixels in a sequence is based on Morton Order.
11. The one or more computer-readable non-transitory storage media of claim 8 , wherein the instructions are configured to further cause the one or more processors to:
determine that a bit length associated with the compression of the block is more than a bit length associated with the plurality of the pixels of the block as uncompressed; and
store the plurality of pixels of the block as uncompressed.
12. The one or more computer-readable non-transitory storage media of claim 8 , wherein the symbol width for encoding each of the non-zero delta values includes an offset.
13. The one or more computer-readable non-transitory storage media of claim 8 , wherein the instructions are configured to further cause the one or more processors to:
modify the compression of the block to be byte-aligned by adding additional bits to the compression of the block.
14. The one or more computer-readable non-transitory storage media of claim 8 , wherein the instructions are configured to further cause the one or more processors to:
decode the compression of the block by processing two or more delta values of the plurality of delta values in parallel.
15. A system comprising: one or more processors; and one or more computer-readable non-transitory storage media in communication with the one or more processors, the one or more computer-readable non-transitory storage media comprising instructions that when executed by the one or more processors, cause the system to:
receive a block comprising a plurality of pixels;
encode the plurality of pixels by:
arranging the plurality of pixels in a sequence;
generating a delta encoding of the plurality of pixels, the delta encoding comprising (a) a base value and (b) a plurality of delta values having non-zero delta values and zero delta values, each delta value representing a difference between a corresponding pixel in the sequence and a previous pixel in the sequence;
generating a symbol mask indicating whether each of the plurality of delta values is zero or non-zero;
determining, based on magnitudes of the non-zero delta values, a symbol width for encoding each of the non-zero delta values;
generating a sequence of symbols that respectively encode the non-zero delta values using the symbol width;
generating a compression of the block by collating the symbol mask, the symbol width, and the sequence of symbols.
16. The system of claim 15 , wherein the plurality of pixels of the block correspond to a single channel of pixel values amongst a plurality channels of pixel values.
17. The system of claim 15 , wherein the instructions, when executed by the one or more processors, further cause the system to:
determine that a bit length associated with the compression of the block is more than a bit length associated with the plurality of the pixels of the block as uncompressed; and
store the plurality of pixels of the block as uncompressed.
18. The system of claim 15 , wherein the symbol width for encoding each of the non-zero delta values includes an offset.
19. The system of claim 15 , wherein the instructions, when executed by the one or more processors, further cause the system to:
modify the compression of the block to be byte-aligned by adding additional bits to the compression of the block.
20. The system of claim 15 , wherein the instructions, when executed by the one or more processors, further cause the system to:
decode the compression of the block by processing two or more delta values of the plurality of delta values in parallel.