Field programmable gate array with external phase-locked loop

1. A method for processing a first serial data stream, using a field programmable gate array system, to generate a second serial data stream, wherein the method comprises the steps of:

(a) receiving, by a deserializer in a field programmable array, a clock signal;

(b) receiving, by the deserializer, the first serial data stream;

(c) generating, by the deserializer, a receiver side clock signal;

(d) converting, by the deserializer, the first serial data stream into a first plurality of parallel data streams;

(e) transmitting, from the deserializer to computational circuitry in the field programmable gate array, the first plurality of parallel data streams;

(f) transmitting, from the deserializer to a phase lock loop of the field programmable gate array system that is not within the field programmable gate array, the receiver side clock signal;

(g) generating, using the phase lock loop, a second clock signal;

(h) generating, within the field programmable gate array, a transmitter side clock signal derived from the second clock signal;

(i) performing, by the computational circuitry, a set of operations on at least a portion of the first plurality of parallel data streams to generate a second plurality of parallel data streams; and

(j) transmitting, from the field programmable gate array system, the second serial data stream, derived from the second plurality of parallel data streams,

wherein said method does not use clock domain crossing operations that delay processing of the first set of parallel data streams.

2. The method of claim 1 , wherein the first serial data stream comprises market data, the second serial data stream comprises order entry data, and the set of operations are associated with a trading algorithm.

3. The method of claim 1 , wherein the first serial data stream includes market data and the second serial data stream includes trading data.

4. The method of claim 1 , wherein the set of operations includes at least one of the following:

(i) an arithmetic operation;

(ii) a logical operation;

(iii) a pipeline operation; and

(iv) a memory access operation.

5. The method of claim 1 , wherein at least a portion of the set of operations performed in step (h) are performed prior to step (g).

6. The method of claim 1 , wherein at least a portion of the set of operations performed in step (h) are performed after step (g).

7. The method of claim 1 , wherein all of the set of operations performed in step (h) are performed after step (g).

8. The method of claim 1 , wherein step (g) further comprises:

(i) generating, by the phase lock loop, a feedback clock signal associated with the transmitter side clock signal by performing the following steps until a first output of a phase detector of the field programmable gate array system is below a first threshold level:

(1) generating, by an adjustable oscillator in the field programmable gate array system, the second clock signal;

(2) generating, by the phase detector, the first output based on a comparison of the receiver side clock signal and the feedback clock signal obtained from the second clock signal;

(3) transmitting, from the phase detector to a phase controller of the field programmable gate array system, the first output;

(4) determining, by the phase controller, interim adjustment information based on the first output; and

(5) transmitting, from the phase controller to the adjustable oscillator, the interim adjustment information;

wherein, the adjustable oscillator adjusts the second clock signal based on the interim adjustment information,

wherein steps (1) through (5) are repeated until the first output of the phase detector is below the first threshold level.

9. The method of claim 1 , wherein the first plurality of data streams has the same number of data streams as the second plurality of data streams.

10. The method of claim 1 , wherein the first plurality of data streams and the second plurality of data streams comprise one of the following:

(i) eight (8) data streams;

(ii) ten (10) data streams;

(iii) sixteen (16) data streams;

(iv) twenty (20) data streams;

(v) thirty-two (32) data streams;

(vi) forty (40) data streams;

(vii) sixty-four (64) data streams;

(viii) eighty (80) data streams;

(ix) one hundred twenty-eight (128) data streams; and

(x) one hundred sixty (160) data streams.

11. The method of claim 1 , wherein the transmitter side clock signal and the receiver side clock signal have the same frequency and phase.

12. The method of claim 1 , wherein the transmitter side clock signal and the receiver side clock signal have the same frequency and different phases.