Cross-coupling connections for stacked field effect transistors
A semiconductor device including a first pair of stacked transistors comprising a first upper transistor and a first lower transistor, a third transistor disposed adjacent to the first lower transistor, the third transistor comprising a gate portion extending from the third transistor gate toward the first pair of stacked transistors, a cross-connection disposed in contact with the gate portion and extending upward, and a gate contact disposed in contact with the cross-connection and a top surface of the first upper transistor.
1 . A semiconductor device comprising:
a first pair of stacked transistors comprising a first upper transistor and a first lower transistor;
a third transistor disposed adjacent to the first lower transistor, the third transistor comprising an electrically conductive gate portion extending from a third transistor gate toward the first pair of stacked transistors;
an electrically conductive cross-connection disposed in contact directly with the electrically conductive gate portion extending upward and
disposed in electrical contact with a top surface of a gate of the first upper transistor; and
a dielectric layer disposed above and in contact with the electrically conductive cross-connection, wherein the dielectric layer covers the upper surface of the electrically conductive cross-connection.
2 . The semiconductor device according to claim 1 , further comprising a fourth transistor stacked upon the third transistor and a second cross-connection between a gate extension of the first lower transistor and the fourth transistor.
3 . The semiconductor device according to claim 1 , wherein the first upper transistor is a first FET (field effect transistor) and the third transistor is a second FET, and wherein the first cross-connection forms a first gate connecting the first FET to the second FET.
4 . The semiconductor device according to claim 1 , wherein the first upper transistor is NFET and the third transistor is PFET.
5 . The semiconductor device according to claim 1 , wherein the first upper transistor is PFET and the third transistor is NFET.
6 . The semiconductor device according to claim 1 , further comprising a bonding dielectric layer between the first upper transistor and the first lower transistor, wherein the cross-connection passes through the bonding dielectric layer.
7 . The semiconductor device according to claim 1 , wherein the gate portion comprises high-k metal gate material which is the same as the third transistor gate.
8 . A semiconductor device comprising:
a first pair of stacked transistors comprising a first upper transistor and a first lower transistor;
a gate cut region disposed adjacent to a gate of the first lower transistor;
a third transistor disposed adjacent to the gate cut region, the third transistor comprising an electrically conductive gate portion extending from a third transistor gate over the gate cut region;
a bonding dielectric layer disposed between the first upper transistor and the first lower transistor;
an electrically conductive cross-connection disposed through the bonding dielectric layer and in contact with the electrically conductive gate portion and a bottom surface of a gate of the first upper transistor; and
a dielectric layer disposed above and in contact with the first upper transistor, wherein the dielectric layer covers the upper surface of the first transistor.
9 . The semiconductor device according to claim 8 , further comprising a fourth transistor stacked upon the third transistor and a second cross-connection between a gate extension of the first lower transistor and the fourth transistor.
10 . The semiconductor device according to claim 9 wherein the bonding dielectric layer separates the third transistor and the fourth transistor; and the second cross-connection passes through the bonding dielectric layer.
11 . The semiconductor device according to claim 8 , wherein the first upper transistor is a first FET (field effect transistor) and the third transistor is a second FET, and wherein the first cross-connection forms a first gate connecting the first FET to the second FET.
12 . The semiconductor device according to claim 8 , wherein the first upper transistor is NFET and the third transistor is PFET.
13 . The semiconductor device according to claim 8 , wherein the first upper transistor is PFET and the third transistor is NFET.
14 . The semiconductor device according to claim 8 , wherein the gate extension comprises high-k metal gate materials which are the same as a third transistor gate.