IP Library Patent Application 17728174
Patent Application
App. No. 17/728,174

SHIELDED FINE-PITCH HIGH-PERFORMANCE IMPEDANCE TUNABLE INTERCONNECT

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Quick Facts
Patent No.
US None
App. No.
17/728,174
Abstract

An apparatus and method for adjusting differential impendence of pins in a socket are described. A socket or test system includes a pin assembly that contains a pin block and pins. The pin block is formed from a material having a first permittivity. The pins include differential pin pairs with a fine pitch and provide electrical contact to an electronic package disposed on the pin block. A volume between each pin of the differential pin pairs or between adjacent pin pairs have a second permittivity that is different than the first permittivity. The volume is filled with air or one or more materials (or air) whose combined permittivity reduces or increases the differential impendence.

Claims (48)

1 . An apparatus for a pin assembly, the apparatus comprising:

a pin block formed from a material having a first permittivity; and

pins disposed in the pin block in a lattice of predetermined fine pitch locations, the pins extending completely through the pin block to provide electrical contact to an electronic package disposed on the pin block, the pins including differential pin pairs, a volume in the pin block having a second permittivity that is less than the first permittivity to reduce a differential impendence of at least some of the differential pin pairs, wherein the volume is disposed between at least some of adjacent pins in the pin block.

2 . The apparatus of claim 1 , wherein the volume is disposed between pins of at least one of the differential pin pairs.

3 . The apparatus of claim 1 , wherein the volume is disposed between adjacent differential pin pairs.

4 . The apparatus of claim 1 , wherein the volume is substantially entirely filled with a substance having the second permittivity.

5 . The apparatus of claim 4 , wherein the second permittivity is about 1 .

6 . The apparatus of claim 1 , wherein:

the volume is partially filled with air and partially filled with a solid, and

a volume adjacent to each pin of the differential pin pairs is filled with air and a volume between the air is filled with the solid.

7 . The apparatus of claim 1 , wherein:

the volume is partially filled with air and partially filled with a solid, and

the solid is the material of the pin block.

8 . The apparatus of claim 1 , wherein:

the volume is partially filled with air and partially filled with a solid, and

the solid is a material has a permittivity between the first permittivity and permittivity of air.

9 . The apparatus of claim 1 , wherein:

the pin block comprises a cavity in which the pins are disposed, the cavity defined by walls connected by a base that retains one end of the pins, and

the apparatus further comprises:

a pin retainer configured to retain another end of the pins, and

a shim disposed between the pin block and the pin retainer, the shim configured to provide mechanical support for the pins.

10 . The apparatus of claim 1 , wherein:

the pin block is formed from a shielding material, and

the volume is disposed between each pin of the differential pin pairs.

11 . The apparatus of claim 1 , wherein:

the pin block is formed from a shielding material, and

the volume is disposed between adjacent pin pairs of the differential pin pairs.

12 . The apparatus of claim 1 , wherein the volume is formed from alternating solid layers of the material and hollow layers of the material.

13 . A testing system comprising:

a socket configured to receive a chip package, the socket including:

a pin block formed from a material having a first permittivity; and

pins disposed in the pin block to contact an electronic package disposed on the pin block, the pins including pairs of differential pins, a volume in the pin block between at least some of the pins having a second permittivity that is different than the first permittivity to adjust a differential impendence of the at least some of the pins; and

a printed circuit board (PCB) on which the socket is disposed, the PCB having a channel for electrically connecting the pins to a device under test.

14 . The testing system of claim 13 , wherein the volume is substantially entirely air.

15 . The testing system of claim 13 , wherein a volume adjacent to each pin is filled with air and a volume between the air is filled with a solid having a permittivity between the first permittivity and permittivity of air.

16 . The testing system of claim 13 , wherein the second permittivity is larger than the first permittivity and excavation of material around the pins in the pin block reduces a dielectric constant to increase the differential impedance of the pins to more closely match a channel impedance.

17 . The testing system of claim 13 , wherein:

the pin block comprises a cavity in which the pins are disposed, the cavity defined by walls connected by a base that retains one end of the pins, and

the socket further comprises:

a pin retainer configured to retain another end of the pins, and

a shim disposed between the pin block and the pin retainer, the shim configured to provide mechanical support for the pins.

18 . A method of fabricating a socket, the method comprising:

forming a pin block from a material having a first permittivity, forming of the pin block comprising:

providing fine pitch openings for pins to extend completely through the pin block at predetermined locations; and

forming a volume between at least some of the openings to have a second permittivity that is less than the first permittivity; and

inserting the pins into the openings to enable electrical contact to an electronic package.

19 . The method of claim 18 , wherein forming the volume between at least some of the openings to have a second permittivity that is less than the first permittivity comprises removing all of the material having the first permittivity from the volume by drilling away the material.

20 . The method of claim 18 , wherein forming the pin block comprises printing alternating thin and hollow layers that contain the openings.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2026
From: INTEL CORPORATION
To: INTEL PRODUCTS IP LLC
Reel/Frame 075991/0981 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 18, 2023
From: FRANCO, ISMAEL; DU, DAQIAO; DEFORD, BRIAN
To: INTEL CORPORATION
Reel/Frame 062409/0477 →