Nanowire/nanosheet device with support portion, method of manufacturing the same, and electronic apparatus

1. A nanowire/nanosheet device comprising:

a substrate;

a first source/drain layer and a second source/drain layer opposite to each other in a first direction on the substrate;

a first nanowire/nanosheet and a second nanowire/nanosheet, wherein the first nanowire/nanosheet and the second nanowire/nanosheet are spaced apart from a surface of the substrate, the first nanowire/nanosheet and the second nanowire/nanosheet extend from the first source/drain layer to the second source/drain layer, respectively, and are arranged adjacent to each other in a direction parallel to the surface of the substrate;

a first support portion connected between the first nanowire/nanosheet and the second nanowire/nanosheet; and

a gate stack extending in a second direction to surround the first nanowire/nanosheet and the second nanowire/nanosheet, wherein the second direction intersects the first direction,

a third nanowire/nanosheet and a fourth nanowire/nanosheet, wherein the third nanowire/nanosheet and the fourth nanowire/nanosheet are spaced apart from the surface of the substrate, the third nanowire/nanosheet and the fourth nanowire/nanosheet extend from the first source/drain layer to the second source/drain layer, respectively, and are arranged adjacent to each other in the direction parallel to the surface of the substrate; and

a second support portion connected between the third nanowire/nanosheet and the fourth nanowire/nanosheet,

wherein the third nanowire/nanosheet is substantially aligned with the first nanowire/nanosheet in a direction perpendicular to the surface of the substrate, the fourth nanowire/nanosheet is substantially aligned with the second nanowire/nanosheet in the direction perpendicular to the surface of the substrate, and the second support portion is substantially aligned with the first support portion in the vertical direction, and

wherein the gate stack further surrounds the third nanowire/nanosheet and the fourth nanowire/nanosheet.

2. The nanowire/nanosheet device according to claim 1 , wherein the first nanowire/nanosheet is substantially coplanar with the second nanowire/nanosheet.

3. The nanowire/nanosheet device according to claim 1 , wherein the first nanowire/nanosheet is substantially coplanar with the second nanowire/nanosheet and the first support portion.

4. The nanowire/nanosheet device according to claim 1 , wherein the first nanowire/nanosheet is integral with the second nanowire/nanosheet and the first support portion.

5. The nanowire/nanosheet device according to claim 4 , wherein when viewed from above, the first nanowire/nanosheet, the second nanowire/nanosheet and the first support portion as a whole has a sheet shape with an opening formed in the sheet shape.

6. The nanowire/nanosheet device according to claim 5 , wherein when viewed from above, the first nanowire/nanosheet, the second nanowire/nanosheet and the first support portion as a whole has a shape of a character “ ” or a shape of a character “ ”.

7. The nanowire/nanosheet device according to claim 5 , wherein the sheet shape has a plurality of openings, and a minimum spacing among the plurality of openings is in a range of 5 nm to 20 nm.

8. The nanowire/nanosheet device according to claim 5 , wherein a plurality of nanowire/nanosheet devices are provided on the substrate, and the openings of at least some of the plurality of nanowire/nanosheet devices are different in at least one of numbers, shapes, sizes and layouts.

9. The nanowire/nanosheet device according to claim 4 , wherein the gate stack surrounds an entirety of the first nanowire/nanosheet, the second nanowire/nanosheet, and the first support portion.

10. The nanowire/nanosheet device according to claim 1 , wherein a minimum spacing between the first nanowire/nanosheet and the second nanowire/nanosheet is in a range of 5 nm to 30 nm.

11. The nanowire/nanosheet device according to claim 1 , wherein the first support portion has a width in a range of 5 nm to 15 nm.

12. An electronic apparatus comprising the nanowire/nanosheet device according to claim 1 .

13. The electronic apparatus according to claim 12 , wherein the electronic apparatus comprises a smart phone, a personal computer, a tablet computer, an artificial intelligence apparatus, a wearable device, or a portable power supply.

14. A method of manufacturing a nanowire/nanosheet device, comprising:

forming a nanowire/nanosheet defining layer on a substrate, wherein the nanowire/nanosheet defining layer is spaced apart from the substrate;

forming a first source/drain layer and a second source/drain layer on two opposite sides of the nanowire/nanosheet defining layer in a first direction, wherein the first source/drain layer and the second source/drain layer are connected to the nanowire/nanosheet defining layer;

patterning the nanowire/nanosheet defining layer into a pattern comprising: a first nanowire/nanosheet and a second nanowire/nanosheet extending from the first source/drain layer to the second source/drain layer, respectively, and a first support portion connected between the first nanowire/nanosheet and the second nanowire/nanosheet;

forming a gate stack on the substrate, wherein the gate stack extends in a second direction intersecting the first direction and surrounds the first nanowire/nanosheet and the second nanowire/nanosheet,

wherein the forming a nanowire/nanosheet defining layer on a substrate, wherein the nanowire/nanosheet defining layer is spaced apart from the substrate comprises:

forming the nanowire/nanosheet defining layer on the substrate, wherein the nanowire/nanosheet defining layer is spaced apart from the substrate and extends in the first direction;

forming a dummy gate on the substrate, wherein the dummy gate extends in the second direction and surrounds the nanowire/nanosheet defining layer; and

patterning the nanowire/nanosheet defining layer by using the dummy gate as a mask.

15. The method according to claim 14 further comprising:

forming a spacer on a sidewall of the dummy gate, wherein the first source/drain layer and the second source/drain layer are formed after the spacer is formed; and

removing the dummy gate, wherein the nanowire/nanosheet defining layer is patterned after the dummy gate is removed, and the gate stack is formed in a space left on an inner side of the spacer by a removal of the dummy gate.

16. The method according to claim 14 wherein the forming the nanowire/nanosheet defining layer comprises:

forming an isolation portion defining layer on the substrate; and

forming a stack of one or more gate defining layers and one or more nanowire/sheet defining layers alternately arranged on the isolation portion defining layer; and

patterning the stack and the isolation portion defining layer to extend in the first direction; and

wherein the forming a dummy gate comprises:

forming another gate defining layer on the substrate to cover the stack and the isolation portion defining layer;

patterning the another gate defining layer into a strip shape extending in the second direction; and

patterning the stack by using the another gate defining layer as a mask, wherein the gate defining layer and the another gate defining layer form the dummy gate.