Semiconductor device including barrier layer between active region and semiconductor layer and method of forming the same
A semiconductor device includes; an active region; an isolation region defining the active region; a barrier layer on the active region; an upper semiconductor layer on the barrier layer; and a gate structure covering an upper surface, a lower surface, and side surfaces of the upper semiconductor layer in a first direction. The first direction is a direction parallel to an upper surface of the active region, and the barrier layer is disposed between the gate structure and the active region.
1. A semiconductor device, comprising:
a substrate;
an active region on the substrate;
an isolation region on the substrate and on side surfaces of the active region;
a first source/drain region and a second source/drain region on the active region and spaced apart from each other;
a barrier layer on and contacting the active region;
upper semiconductor layers on the barrier layer and spaced apart from each other in a vertical direction; and
a gate structure covering an upper surface, a lower surface, and side surfaces of each of the upper semiconductor layers in a first direction and extending on the isolation region,
wherein the vertical direction is perpendicular to an upper surface of the substrate,
wherein the first direction is parallel to the upper surface of the substrate,
wherein a material of the barrier layer is different from a material of the upper semiconductor layers,
wherein the barrier layer and the upper semiconductor layers are between the first source/drain region and the second source/drain region,
wherein the barrier layer includes a first side surface contacting the first source/drain region and a second side surface contacting the second source/drain region,
wherein the barrier layer further includes a third side surface and a fourth side surface,
wherein at least a portion of each of the third and fourth side surfaces of the barrier layer contacts the gate structure, and
wherein a lower surface of the gate structure adjacent to the barrier layer is at a higher level than a lower surface of the barrier layer.
2. The semiconductor device of claim 1 , wherein lower surfaces of the first and second source/drain regions are at a lower level than the lower surface of the barrier layer.
3. The semiconductor device of claim 1 , wherein each of the third and fourth side surfaces of the barrier layer includes a first side portion contacting the gate structure and a second side portion contacting the isolation region.
4. The semiconductor device of claim 1 , wherein the barrier layer includes a barrier impurity element, and wherein the upper semiconductor layers do not include the barrier impurity element.
5. The semiconductor device of claim 4 , wherein the barrier impurity element includes at least one of oxygen (O) and carbon (C).
6. The semiconductor device of claim 1 , wherein an upper surface of the barrier layer contacts the gate structure.
7. The semiconductor device of claim 1 , further comprising:
a lower semiconductor layer between the gate structure and the barrier layer,
wherein a lower surface of the lower semiconductor layer contacts the barrier layer,
wherein an upper surface of the lower semiconductor layer contacts the gate structure, and
wherein a material of the lower semiconductor layer is different from the material of the barrier layer.
8. The semiconductor device of claim 1 , wherein the active region includes side surfaces aligned with the third and fourth side surfaces of the barrier layer.
9. The semiconductor device of claim 1 , wherein a thickness of the barrier layer is different from a thickness of each of the upper semiconductor layers.
10. A semiconductor device comprising:
a substrate;
an active region on the substrate;
an isolation region on the substrate and on side surfaces of the active region;
a first source/drain region and a second source/drain region on the active region and spaced apart from each other;
a barrier layer on and contacting the active region;
upper semiconductor layers on the barrier layer and spaced apart from each other in a vertical direction; and
a gate structure covering an upper surface, a lower surface, and side surfaces of each of the upper semiconductor layers in a first direction and extending on the isolation region,
wherein the vertical direction is perpendicular to an upper surface of the substrate,
wherein the first direction is parallel to the upper surface of the substrate,
wherein a material of the barrier layer is different from a material of the upper semiconductor layers,
wherein the barrier layer and the upper semiconductor layers are between the first source/drain region and the second source/drain region,
wherein the barrier layer includes a first side surface contacting the first source/drain region and a second side surface contacting the second source/drain region,
wherein the barrier layer further includes a third side surface and a fourth side surface,
wherein at least a portion of each of the third and fourth side surfaces of the barrier layer contacts the gate structure, and
wherein the barrier layer further includes a first barrier portion between the active region and the first source/drain region, and a second barrier portion between the active region and the second source/drain region.
11. The semiconductor device of claim 10 , wherein a thickness of a portion of the barrier layer between the gate structure and the active region is greater than a thickness of each of the first and second barrier portions.
12. The semiconductor device of claim 10 , wherein a lower surface of the gate structure adjacent to the barrier layer is at a higher level than a lower surface of the barrier layer.
13. The semiconductor device of claim 10 , wherein an upper surface of the barrier layer contacts the gate structure.
14. The semiconductor device of claim 10 , further comprising:
a lower semiconductor layer between the gate structure and the barrier layer,
wherein a lower surface of the lower semiconductor layer contacts the barrier layer,
wherein an upper surface of the lower semiconductor layer contacts the gate structure, and
wherein a material of the lower semiconductor layer is different from the material of the barrier layer.
15. The semiconductor device of claim 10 , wherein the active region includes side surfaces aligned with the third and fourth side surfaces of the barrier layer.
16. The semiconductor device of claim 10 , wherein a thickness of the barrier layer is different from a thickness of each of the upper semiconductor layers.
17. The semiconductor device of claim 10 , wherein a lower surface of the gate structure is at a lower level than a lower surface of the barrier layer.