Method for fabricating semiconductor device with capacitors having shared electrode

1. A method for fabricating a semiconductor device, comprising:

providing a substrate;

forming a first trench in the substrate;

doping sidewalls and a bottom surface of the first trench to form a bottom conductive structure;

forming a first insulating layer on the bottom conductive structure and in the first trench;

forming first spacers on sidewalls of the shared conductive layer;

forming a shared conductive layer on the first insulating layer and the first spacers after forming the first spacers;

forming a second insulating layer on the shared conductive layer;

forming a top conductive layer on the second insulating layer; and

forming a connection structure electrically connecting the bottom conductive structure and the top conductive layer;

wherein the bottom conductive structure, the first insulating layer, and the shared conductive layer together configure a first capacitor unit, and the shared conductive layer, the second insulating layer, and the top conductive layer together configure a second capacitor unit.

2. The method for fabricating the semiconductor device of claim 1 , wherein the substrate and the bottom conductive structure have opposite electrical type.

3. The method for fabricating the semiconductor device of claim 2 , wherein an aspect ratio of the first trench is between about 1:6 and about 1:20.

4. The method for fabricating the semiconductor device of claim 3 , wherein the first insulating layer is formed of an insulating material having a dielectric constant of about 4.0 or greater.

5. The method of claim 1 , wherein a width of the second insulating layer is greater than a width of the shared conductive layer.

6. The method of claim 5 , wherein the connection structure comprising a first conductive via electrically connecting the top conductive layer, a second conductive via electrically connecting the bottom conductive structure, and a conductive line horizontally on the first conductive via and the second conductive via and electrically connect the first conductive via and the second conductive via.

7. The method of claim 6 , further comprising: forming an assistant conductive layer between the second conductive via and the bottom conductive structure, wherein the assistant conductive layer is formed of titanium silicide, nickel silicide, nickel platinum silicide, tantalum silicide, or cobalt silicide.

8. The method of claim 7 , wherein a thickness of the assistant conductive layer is between about 2 nm and about 20 nm.

9. The method of claim 1 , wherein the first insulating layer is an oxide-nitride-oxide structure.

10. The method of claim 9 , further comprising: forming an interfacial layer between the bottom conductive structure and the first insulating layer, wherein the interfacial layer is formed of silicon oxide.

11. The method of claim 10 , wherein a thickness of the interfacial layer is between about 7 angstroms and about 12 angstroms.

12. The method of claim 9 , further comprising: forming a first barrier layer between the first insulating layer and the shared conductive layer, wherein the first barrier layer is formed of titanium, titanium nitride, titanium silicon nitride, tantalum, tantalum nitride, tantalum silicon nitride, or a combination thereof.

13. The method of claim 12 , wherein a thickness of the first barrier layer is between about 10 angstroms and about 15 angstroms.

14. The method of claim 9 , wherein a thickness of the first insulating layer is about 10 angstroms and about 1000 angstroms.

15. The method of claim 5 , wherein a width of the top conductive layer is less than the width of the shared conductive layer.

16. The method of claim 1 , wherein the shared conductive layer comprises a connection portion above a top surface of the substrate and a bottom portion extending downwardly to the substrate.