Method and system for replacement of memory cells

1. A memory system, comprising:

a compare circuit configured to determine, in response to a number of detected error bits in a read data from a first memory array, whether a fail word address associated with the detected error bits is in an error table; and

a control circuit configured to increment a counter value corresponding to the fail word address when the fail word address is in the error table, and further configured to compare the counter value with a threshold value to replace memory locations, corresponding to the fail word address, in the first memory array with backup memory locations in a second memory array.

2. The memory system of claim 1 , further comprising:

an error correction code circuit configured to correct the number of the detected error bits in the read data and configured to generate an error determination signal corresponding to the fail word address.

3. The memory system of claim 1 , further comprising:

a replace circuit configured to receive the fail word address from the control circuit to replace the memory locations, corresponding to the fail word address, in the first memory array with the backup memory locations in the second memory array.

4. The memory system of claim 1 , wherein the control circuit is further configured to record the fail word address and the counter value in the error table.

5. The memory system of claim 1 , further comprising:

a storage circuit configured to receive the fail word address to update a repair information; and

a replace circuit configured to perform a replacing operation to replace the memory locations based on the repair information.

6. The memory system of claim 5 , further comprising:

a processing unit configured to determine a period of the replacing operation.

7. The memory system of claim 1 , further comprising:

an error correction code circuit configured to correct a predetermined number of error bits in the number of the detected error bits of the read data, wherein the predetermined number and the number of the detected error bits are different from each other.

8. The memory system of claim 1 , further comprising:

a storage unit configured to store the error table,

wherein the control circuit is further configured to obtain the counter value from the error table in the storage unit by sending a fail count signal to the storage unit.

9. A method, comprising:

recording a fail word address in an error table;

adjusting a counter value associated with the fail word address, wherein the counter value indicates that a number of times the fail word address is recorded; and

replacing a plurality of memory locations corresponding to the fail word address with a plurality of backup memory locations.

10. The method of claim 9 , further comprising:

correcting a maximum N number of error bits in a read data corresponding to the fail word address; and

setting a number M to record the fail word address associated with M error bits,

wherein N and M are positive integers, and N is different from M.

11. The method of claim 10 , further comprising:

adjusting the number M, in response to a control signal, to be equal to N.

12. The method of claim 9 , wherein adjusting the counter value associated with the fail word address comprises:

determining whether the fail word address matches one of word addresses in the error table; and

in response to the determination, incrementing the counter value corresponding to the fail word address.

13. The method of claim 9 , further comprising:

after replacing, removing the fail word address from the error table.

14. The method of claim 9 , further comprising:

comparing the counter value with a threshold value; and

when the counter value is greater than the threshold value, updating a repair information with the fail word address.

15. A method, comprising:

comparing a received fail word address with a plurality of fail word addresses in an error table to increment a corresponding counter value, associated with the received fail word address, in a plurality of counter values;

sorting the plurality of fail word addresses based on the plurality of counter values; and

replacing memory locations corresponding to a top fail word address, of the plurality of fail word addresses, in a top entry of the error table.

16. The method of claim 15 , wherein the corresponding counter value indicates how many times the corresponding fail word address is recorded in the error table.

17. The method of claim 15 , wherein replacing the memory locations corresponding to the top fail word address further comprises:

replacing the memory locations periodically with a plurality of backup memory locations.

18. The method of claim 15 , further comprising:

counting the plurality of counter values associated with the plurality of fail word addresses,

wherein comparing the received fail word address with the plurality of fail word addresses comprises:

when the received fail word address is not in the error table, recording the received fail word address in the error table and setting the corresponding counter value being 1 .

19. The method of claim 15 , further comprising:

updating a repair information with the top fail word address.

20. The method of claim 15 , further comprising:

removing the top fail word address after replacing the memory locations corresponding to the top fail word address.