Memory system for executing a target operation based on a program state of a super memory block and operating method thereof
The embodiments of the present disclosure relate to a memory system and operating method thereof. According to embodiments of the present disclosure, the memory system may include i) a memory device including a plurality of memory blocks each including a plurality of pages, and ii) a memory controller configured to monitor a program operation on a first super memory block among a plurality of super memory blocks each including at least one of the plurality of memory blocks, and execute a target operation on the first super memory block based on the state of the first super memory block when it is determined that the program operation on the first super memory block has not been executed for a preset time period from a preset reference time point.
1. A memory system comprising:
a memory device including a plurality of memory blocks each including a plurality of pages; and
a memory controller configured to:
monitor a program operation on a first super memory block among a plurality of super memory blocks each including at least one of the plurality of memory blocks, and
execute a target operation on the first super memory block based on the state of the first super memory block when it is determined that the program operation on the first super memory block has not been executed for a preset time period from a preset reference time point,
wherein the memory controller is further configured to set the reference time point as a time point at which the memory system enters an idle state or a low power mode.
2. The memory system of claim 1 , wherein the memory controller is further configured to determine, as the target operation, one of an operation of migrating, to the first super memory block, a valid data unit of a preset size stored in a second super memory block among the plurality of super memory blocks, an operation of migrating, to all erased pages included in the first super memory block, all or a part of valid data stored in the second super memory block, and an operation of migrating, to the second super memory block, all valid data stored in the first super memory block.
3. The memory system of claim 2 , wherein the memory controller determines, as the target operation:
the operation of migrating, to the first super memory block, the valid data unit in the second super memory block when a number of erased pages included in the first super memory block is greater than or equal to a threshold number, and
the operation of migrating, to all erased pages included in the first super memory block, all or the part of valid data stored in the second super memory block when the number of erased pages included in the first super memory block is less than the threshold number.
4. The memory system of claim 3 ,
wherein the memory controller is further configured to determine the preset size of the valid data unit in proportion to a size of the first super memory block, and
wherein the size of the first super memory block is determined based on a number of memory blocks included in the first super memory block.
5. The memory system of claim 4 , wherein the memory controller executes, as the target operation, the operation of migrating the valid data unit from the second super memory block to the first super memory block by reading the valid data unit from the second super memory block by an interleaved manner.
6. The memory system of claim 3 , wherein the memory controller executes, as the target operation, the operation of migrating the valid data unit from the second super memory block to the first super memory block by programming the valid data unit from a position next to a most recently programmed position in the first super memory block.
7. The memory system of claim 2 , wherein the memory controller determines, as the target operation, the operation of migrating, to the second super memory block, all valid data stored in the first super memory block when the first super memory block is a super memory block in which data is sequentially programmed according to an order of a logical address.
8. The memory system of claim 7 , wherein the memory controller is further configured to set, after the executing of the target operation, the second super memory block as a super memory block in which data is sequentially programmed according to an order of a logical address.
9. The memory system of claim 1 , wherein the memory controller is further configured to program, after the executing of the target operation, data requested to be written from outside the memory system into an erased page included in the first super memory block.
10. An operating method of a memory system, the operating method comprising:
monitoring a program operation on a first super memory block among a plurality of super memory blocks each including at least one of a plurality of memory blocks each including a plurality of pages;
determining whether the program operation for the first super memory block is executed for a preset time period from a preset reference time point; and
executing a target operation on the first super memory block based on the state of the first super memory block when it is determined that the program operation on the first super memory block has not been executed for the preset time period from the preset reference time point,
wherein the reference time point is a time point at which the memory system enters an idle state or a low power mode.
11. The operating method of claim 10 , further comprising determining, as the target operation, one of an operation of migrating, to the first super memory block, a valid data unit of a preset size stored in a second super memory block among the plurality of super memory blocks, an operation of migrating, to all erased pages included in the first super memory block, all or a part of valid data stored in the second super memory block, and an operation of migrating, to the second super memory block, all valid data stored in the first super memory block.
12. The operating method of claim 11 , wherein the determining includes determining, as the target operation,
the operation of migrating, to the first super memory block, the valid data unit in the second super memory block when a number of erased pages included in the first super memory block is greater than or equal to a threshold number, and
the operation of migrating, to all erased pages included in the first super memory block, all or the part of valid data stored in the second super memory block when the number of erased pages included in the first super memory block is less than the threshold number.
13. The operating method of claim 12 ,
further comprising determining the preset size of the valid data unit in proportion to a size of the first super memory block, and
wherein the size of the first super memory block is determined based on a number of memory blocks included in the first super memory block.
14. The operating method of claim 13 , wherein the operation of migrating the valid data unit from the second super memory block to the first super memory block, as the target operation, includes reading the valid data unit from the second super memory block by an interleaved manner.
15. The operating method of claim 12 , wherein the operation of migrating the valid data unit from the second super memory block to the first super memory block, as the target operation, includes programming the valid data unit from a position next to a most recently programmed position in the first super memory block.
16. The operating method of claim 11 , wherein the determining includes determining, as the target operation, the operation of migrating, to the second super memory block, all valid data stored in the first super memory block when the first super memory block is a super memory block in which data is sequentially programmed according to an order of a logical address.
17. The operating method of claim 16 , further comprising setting, after the executing of the target operation, the second super memory block as a super memory block in which data is sequentially programmed according to an order of a logical address.
18. The operating method of claim 10 , further comprising programming, after the executing of the target operation, data requested to be written from outside the memory system into an erased page included in the first super memory block.