IP Library › Granted Patent US 11,626,887
Granted Patent B1
US 11,626,887 · App. 17/743,307 · Granted Apr 11, 2023

Byte-based error correction to improve for wireless networks

Inventors: Anand Chandrasekher (Saratoga, CA); Ravikiran Gopalan (Cupertino, CA); Arman Rahimzamani (San Jose, CA)
Assignee: Aira Technologies, Inc.
H03M13/09H03M13/611H04L1/0061
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Quick Facts
Patent No.
US 11,626,887
App. No.
17/743,307
Granted
Apr 11, 2023
Kind
B1
Abstract

Improved error correction systems and methods for wireless networks are described herein. A method can include generating a first cyclic redundancy code (CRC) for a payload of a data packet by executing cycles for sets of input bytes from the payload using a CRC algorithm so as to reduce a number of the cycles required to generate the first CRC when compared to generating the first CRC from individual bits of the payload, appending the first CRC to the payload of the data packet, and transmitting the data packet over a wireless link from a source to a sink.

Claims (51)

1. A method comprising:

generating a first cyclic redundancy code (CRC) for a payload of a data packet by executing cycles for sets of input bytes from the payload using a CRC algorithm so as to reduce a number of the cycles required to generate the first CRC when compared to generating the first CRC from individual bits of the payload;

for each of the sets of input bytes, shifting the first CRC leftward by a size value for the sets of input bytes;

appending the first CRC to the payload of the data packet; and

transmitting the data packet, including the first CRC appended to the payload of the data packet, over a wireless link from a source to a sink.

2. The method according to claim 1 , wherein each of the sets of input bytes comprises at least eight bits.

3. The method according to claim 1 , further comprising initializing a CRC register with an initial input.

4. The method according to claim 1 , further comprising:

storing a leftmost one of each of the sets of input bytes as a shifted byte set;

precomputing combinations of logical values and shift combinations for updating the first CRC; and

storing the combinations of logical values and shift combinations in memory.

5. The method according to claim 4 , further comprising updating the first CRC by performing a logical operation on each of the sets of input bytes with the combinations of logical values and shift combinations stored in the memory.

6. The method according to claim 1 , further comprising:

calculating a second CRC by the sink, the sink comparing the second CRC with the first CRC; and

transmitting a message to the source over the wireless link that indicates whether the second CRC calculated by the sink matches the first CRC by the source.

7. A system comprising:

a source configured to:

generate a first cyclic redundancy code (CRC) for a payload of a data packet by executing cycles for sets of input bytes from the payload using a CRC algorithm so as to reduce a number of the cycles required to generate the first CRC when compared to generating the first CRC from individual bits of the payload;

for each of the sets of input bytes, shifting the first CRC leftward by a size value for the sets of input bytes;

append the first CRC to the payload of the data packet; and

transmit the data packet, including the first CRC appended to the payload of the data packet, over a wireless link; and

a sink configured to:

calculate a second CRC by the sink;

compare the second CRC with the first CRC; and

transmit a message to the source over the wireless link that indicates whether the second CRC calculated by the sink matches the first CRC by the source.

8. The system according to claim 7 , wherein each of the sets of input bytes comprises at least eight bits.

9. The system according to claim 7 , wherein the source is configured to initialize a CRC register with an initial input.

10. The system according to claim 7 , in wherein the source is configured to:

store a leftmost one of each of the sets of input bytes as a shifted byte set;

precompute combinations of logical values and shift combinations for updating the first CRC; and

store the combinations of logical values and shift combinations in memory.

11. The system according to claim 10 , wherein the source is configured to update the first CRC by performing a logical operation on each of the sets of input bytes with the combinations of logical values and shift combinations stored in the memory.

12. A method comprising:

generating a first cyclic redundancy code (CRC) by executing cycles for sets of input bytes from a payload by processing an initialized CRC register in combination with pre-computed values stored in a lookup table;

initializing a CRC register with an initial input;

for each of the sets of input bytes, shifting the first CRC leftward by a size value for the sets of input bytes;

appending the first CRC to the payload of a data packet; and

transmitting the data packet, including the first CRC appended to the payload of the data packet, over a wireless link from a source to a sink.

13. The method according to claim 12 , wherein each of the sets of input bytes comprises at least eight bits.

14. The method according to claim 12 , further comprising:

storing a leftmost one of each of the sets of input bytes as a shifted byte set;

precomputing combinations of logical values and shift combinations for updating the first CRC; and

storing the combinations in the lookup table in memory.

15. The method according to claim 14 , further comprising updating the first CRC by performing a logical operation on each of the sets of input bytes with the combinations stored in the memory.

16. The method according to claim 15 , further comprising calculating a second CRC by the sink, the sink comparing the second CRC with the first CRC.

17. The method according to claim 16 , further comprising transmitting a message to the source over the wireless link that indicates whether the second CRC calculated by the sink matches the first CRC by the source.

18. A method comprising:

generating a first cyclic redundancy code (CRC) for a payload of a data packet by executing cycles for sets of input bytes from the payload using a CRC algorithm so as to reduce a number of the cycles required to generate the first CRC when compared to generating the first CRC from individual bits of the payload;

updating the first CRC by performing a logical operation on each of the sets of input bytes with precomputed combinations of logical values and shift combinations stored in memory;

appending the updated first CRC to the payload of the data packet; and

transmitting the data packet, including the updated first CRC appended to the payload of the data packet, over a wireless link from a source to a sink.

Assignments (2)
CHANGE OF ADDRESS Recorded Jul 20, 2023
From: AIRA TECHNOLOGIES, INC.
To: AIRA TECHNOLOGIES, INC.
Reel/Frame 064353/0359 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 12, 2022
From: CHANDRASEKHER, ANAND; GOPALAN, RAVIKIRAN; RAHIMZAMANI, ARMAN
To: AIRA TECHNOLOGIES, INC.
Reel/Frame 060482/0326 →