Low density parity check decoder
A method and system for decoding low density parity check (“LDPC”) codes. An LDPC code decoder includes LDPC decoding circuitry comprising a Q message generator and a P sum adder array. The Q message generator combines an R message from a previous iteration with a P message to produce a Q message. The P sum adder array adds the P message to a difference of an R message from a current iteration and the R message from the previous iteration to produce an updated P message.
1. A method for decoding a low density parity check (LDPC) code, comprising:
routing, by circuitry and to a Q message generator:
a P message generated for a layer of an LDPC parity check matrix processed prior to a most recently processed layer of the LDPC parity check matrix for use with a first block of a currently processed layer of the LDPC parity check matrix,
wherein the first block is dependent on a result of the most recently processed layer that is unavailable at a time that the first block is being processed,
wherein the circuitry comprises an array of final state register banks, each bank comprising a plurality of registers for storing final state data for a layer of the LDPC parity check matrix.
2. The method of claim 1 , further comprising the circuitry routing, to the Q message generator:
a P message generated for a second block of the LDPC parity check matrix for use with a third block of the currently processed layer of the LDPC parity check matrix;
wherein the third block is dependent on a result of the second block that is available at a time that the third block is being processed; and
the third block and the second block are in a same block column.
3. The method of claim 1 , further comprising the circuitry selecting one of an updated P message and a channel log-likelihood ratio (LLR) for storage in a P memory, wherein the channel LLR is selected to initialize decoding.
4. The method of claim 1 , wherein the circuitry comprises a P sum adder, and further comprising the P sum adder adding a P message read from a P memory to a difference of an R message from a current iteration and an R message from the previous iteration to produce an updated P message.
5. The method of claim 1 , wherein the circuitry comprises a control unit, and further comprising the control unit controlling the operation of the decoder and the circuitry decoding multiple code rates by changing LDPC code parameters stored in the control unit.
6. The method of claim 5 , further comprising the control unit scheduling no processing of zero blocks of the LDPC parity check matrix.
7. The method of claim 5 , further comprising the control unit causing the circuitry to update the P message based on a determination of a final state for each layer.
8. The method of claim 1 , wherein the circuitry further comprises a multiplexer, and further comprising the multiplexer selecting one of a channel log-likelihood ratio (LLR) value and an updated P message to input to a permuter, and further comprising the multiplexer selecting the channel LLR value to initialize the decoder.
9. The method of claim 1 , wherein the circuitry further comprises a Q message memory and a multiplexer, and further comprising the multiplexer selecting one of a channel log-likelihood ratio (LLR) values and a Q message to input to the Q message memory, and further comprising the multiplexer selecting the channel LLR value to initialize the decoder.
10. The method of claim 1 , further comprising the circuitry selecting an R message from a plurality of previously generated possible R messages based on at least a message index value.
11. A method for decoding a low density parity check (LDPC) code, comprising:
routing, by circuitry and to a Q message generator:
a P message generated for a first non-zero block of an LDPC matrix for use with a second non-zero block of the LDPC matrix based on a P message from a third non-zero block being unavailable at a time that the second non-zero block is being processed,
wherein the first non-zero block, the second non-zero block and the third non-zero block are in a same block column of the LDPC matrix, and the third non-zero block is an only non-zero block between the first non-zero block and the second non-zero block in the block column;
selecting, by the circuitry, one of an updated P message and a channel log-likelihood ratio (LLR) for storage in a P memory; and
selecting, by the circuitry, the channel LLR to initialize decoding.
12. The method of claim 11 , further comprising the circuitry routing, to the Q message generator:
a P message generated for a fourth non-zero block of the LDPC matrix for use with a fifth non-zero block of the LDPC matrix based on a P message from the fourth non-zero block being available at a time that the fifth non-zero block is being processed; and
wherein the fourth non-zero block and fifth non-zero block are in a same block column, and there is no non-zero block between the fourth non-zero block and the fifth non-zero block in the block column.
13. The method of claim 11 , further comprising the circuitry routing, to the Q message generator:
a P message generated for the third non-zero block of the LDPC matrix for use with the second non-zero block of the LDPC matrix based on the P message from the third non-zero block being available at a time that the second non-zero block is being processed.
14. The method of claim 11 , wherein the circuitry further comprises a P sum adder, and further comprising the P sum adder adding a P message read from a P memory to a difference of an R message from a current iteration and an R message from the previous iteration to produce the updated P message.
15. The method of claim 11 , further comprising the circuitry selecting an R message from a plurality of previously generated possible R messages based on at least a message index value.
16. The method of claim 11 , wherein the circuitry comprises an array of final state register banks, each bank comprising a plurality of registers storing final state data for a layer of the LDPC matrix.
17. The method of claim 11 , wherein the circuitry further comprises a control unit, and further comprising the control unit controlling the operation of the decoder, and further comprising the circuitry decoding multiple code rates by changing LDPC code parameters stored in the control unit.
18. The method of claim 17 , further comprising the control unit scheduling no processing of zero blocks of the LDPC matrix.
19. The method of claim 17 , further comprising the control unit causing the circuitry to update the P message based on a determination of a final state for each layer.
20. The method of claim 11 , wherein the circuitry further comprises a multiplexer, and further comprising the multiplexer selecting one of a channel log-likelihood ratio (LLR) value and a P message to input to a permuter, and further comprising the multiplexer selecting the channel LLR value to initialize the decoder.
21. The method of claim 11 , wherein the circuitry further comprises a Q message memory and a multiplexer, and further comprising the multiplexer selecting one of a channel log-likelihood ratio (LLR) value and a Q message to input to the Q message memory, and further comprising the multiplexer selecting the channel LLR value to initialize the decoder.
22. A method for decoding a low density parity check (LDPC) code, comprising:
selectably processing, by an array of reconfigurable minimum finder units in LDPC decoding circuitry, a first plurality (K1) of edges of a first plurality (M1) of check nodes of a first LDPC matrix;
selectably processing, by the array, a second plurality (K2) of edges of a second plurality (M2) of check nodes of a second LDPC matrix, wherein K1 is less than K2, M1 is greater than M2, and a product of K1 and M1 is equal to a product of K2 and M2; and
storing, by a plurality of registers in each bank of an array of final state register banks in the circuitry, final state data for a layer of one of the first LDPC matrix and the second LDPC matrix.
23. The method of claim 22 , wherein the first LDPC matrix and the second LDPC matrix are the same.
24. The method of claim 22 , wherein the circuitry comprises a P memory, and further comprising the circuitry selecting one of an updated P message and a channel log-likelihood ratio (LLR) for storage in the P memory, and further comprising the circuitry selecting the channel LLR to initialize decoding.
25. The method of claim 22 , further comprising the circuitry selecting an R message from a plurality of previously generated possible R messages based on at least a message index value.
26. The method of claim 22 , wherein the circuitry further comprises a control unit, and further comprising the control unit controlling the operation of the decoder, and further comprising the circuitry decoding multiple code rates by changing LDPC code parameters stored in the control unit.
27. The method of claim 26 , further comprising the control unit scheduling no processing of zero blocks of an LDPC parity check matrix.
28. The method of claim 26 , further comprising the control unit causing the circuitry to update a P message based on a determination of a final state for each layer.
29. The method of claim 22 , wherein the circuitry further comprises a permuter and a multiplexer, and further comprising the multiplexer selecting one of a channel log-likelihood ratio (LLR) value and a P message to input to the permuter, and further comprising the multiplexer selecting the channel LLR value to initialize the decoder.
30. The method of claim 22 , wherein the circuitry further comprises a Q message memory and a multiplexer, and further comprising the multiplexer selecting one of a channel log-likelihood ratio (LLR) value and a Q message to input to the Q message memory, and further comprising the multiplexer selecting the channel LLR value to initialize the decoder.